ProASICPLUS Flash Family FPGAs v5.9 1-3 Live at Power-Up The Ac" />
參數資料
型號： APA750-PQG208I
廠商： Microsemi SoC
文件頁數： 146/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 750K 208-PQFP
標準包裝： 24
系列： ProASICPLUS
RAM 位總計： 147456
輸入/輸出數： 158
門數： 750000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 208-BFQFP
供應商設備封裝： 208-PQFP（28x28）
ProASICPLUS Flash Family FPGAs
v5.9
1-3
Live at Power-Up
The Actel flash-based ProASICPLUS devices support
Level 0 of the live at power-up (LAPU) classification
standard. This feature helps in system component
initialization,
executing
critical
tasks
before
the
processor wakes up, setting up and configuring memory
blocks, clock generation, and bus activity management.
The LAPU feature of flash-based ProASICPLUS devices
greatly simplifies total system design and reduces total
system cost, often eliminating the need for complex
programmable logic device (CPLD) and clock generation
PLLs that are used for this purpose in a system. In
addition, glitches and brownouts in system power will
not corrupt the ProASICPLUS device's flash configuration,
and unlike SRAM-based FPGAs, the device will not have
to be reloaded when system power is restored. This
enables the reduction or complete removal of the
configuration
PROM,
expensive
voltage
monitor,
brownout detection, and clock generator devices from
the PCB design. Flash-based ProASICPLUS devices simplify
total system design, and reduce cost and design risk,
while increasing system reliability and improving system
initialization time.
Flash Switch
Unlike SRAM FPGAs, ProASICPLUS uses a live-at-power-up
ISP flash switch as its programming element.
In the ProASICPLUS flash switch, two transistors share the
floating
gate,
which
stores
the
programming
information. One is the sensing transistor, which is only
used for writing and verification of the floating gate
voltage. The other is the switching transistor. It can be
used in the architecture to connect/separate routing nets
or to configure logic. It is also used to erase the floating
Logic Tile
The logic tile cell (Figure 1-3) has three inputs (any or all
of which can be inverted) and one output (which can
connect to both ultra-fast local and efficient long-line
routing resources). Any three-input, one-output logic
function (except a three-input XOR) can be configured as
one tile. The tile can be configured as a latch with clear
or set or as a flip-flop with clear or set. Thus, the tiles can
flexibly map logic and sequential gates of a design.
Figure 1-3 Core Logic Tile
Local Routing
In 1
In 2 (CLK)
In 3 (Reset)
Efficient Long-Line Routing
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相關代理商/技術參數
參數描述
APA750-PQGB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA750-PQGES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA750-PQGI 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA750-PQGM 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA750-PQGPP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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