ProASICPLUS Flash Family FPGAs 2- 28 v5.9 Calculating Typical Power Dissipation " />
參數(shù)資料
型號： APA600-PQG208
廠商： Microsemi SoC
文件頁數(shù)： 111/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 600K 208-PQFP
標準包裝： 24
系列： ProASICPLUS
RAM 位總計： 129024
輸入/輸出數(shù)： 158
門數(shù)： 600000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 208-BFQFP
供應商設備封裝： 208-PQFP（28x28）
ProASICPLUS Flash Family FPGAs
2- 28
v5.9
Calculating Typical Power Dissipation
ProASICPLUS device power is calculated with both a static and an active component. The active component is a function
of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following
formula:
Total Power Consumption—Ptotal
Ptotal = Pdc + Pac
where:
Global Clock Contribution—Pclock
Pclock, the clock component of power dissipation, is given by the piece-wise model:
for R < 15000 the model is: (P1 + (P2*R) – (P7*R2)) * Fs (lightly-loaded clock trees)
for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees)
where:
Storage-Tile Contribution—Pstorage
Pstorage, the storage-tile (Register) component of AC power dissipation, is given by
Pstorage = P5 * ms * Fs
where:
Pdc =
7 mW for the APA075
8 mW for the APA150
11 mW for the APA300
12 mW for the APA450
12 mW for the APA600
13 mW for the APA750
19 mW for the APA1000
Pdc includes the static components of PVDDP + PVDD + PAVDD
Pac =Pclock + Pstorage + Plogic + Poutputs + Pinputs + Ppll + Pmemory
P1
= 100 W/MHz is the basic power consumption of the clock tree per MHz of the clock
P2
= 1.3 W/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of the
clock
P7
= 0.00003 W/MHz is a correction factor for partially-loaded clock trees
P10
= 6850 W/MHz is the basic power consumption of the clock tree per MHz of the clock
P11
= 0.4 W/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of
the clock
R
= the number of storage tiles clocked by this clock
Fs
= the clock frequency
P5
=
1.1 W/MHz is the average power consumption of a storage tile per MHz of its output toggling rate.
The maximum output toggling rate is Fs/2.
ms
=
the number of storage tiles (Register) switching during each Fs cycle
Fs
=
the clock frequency
相關PDF資料
PDF描述
M1AFS1500-1FG676 IC FPGA 8MB FLASH 1.5M 676-FBGA
AT25128B-SSHL-B IC EEPROM 128KBIT 20MHZ 8SOIC
AFS1500-1FG676 IC FPGA 8MB FLASH 1.5M 676-FBGA
AT88SC12816C-PU IC EEPROM 128KBIT 1.5MHZ 8DIP
M1AFS1500-1FGG676 IC FPGA 8MB FLASH 1.5M 676-FBGA
相關代理商/技術參數(shù)
參數(shù)描述
APA600-PQG208A 功能描述:IC FPGA PROASIC+ 600K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）
APA600-PQG208I 功能描述:IC FPGA PROASIC+ 600K 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）
APA600-PQG208M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um Technology 2.5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 600K GATES 180MHZ 0.22UM 2.5V 208PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 158 I/O 208PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA PROASIC+ 600K 208PQFP
APA600-PQGB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
APA600-PQGES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*