ProASICPLUS Flash Family FPGAs 2- 6 v5.9 Input/Output Blocks To" /> 
  • <em id="tq2my"></em>
    <pre id="tq2my"></pre>
    <wbr id="tq2my"><menuitem id="tq2my"><abbr id="tq2my"></abbr></menuitem></wbr>
      • <label id="tq2my"><td id="tq2my"></td></label>
              


      
    



      

      
  
      
    
    
    
      
      
    
      
  
      
  
  

      





 
 




 
 


      

    
      


      參數(shù)資料
      

      


      


      
型號：
APA600-BG456I

      

      
廠商：
Microsemi SoC

      

      
文件頁數(shù)：
68/178頁

      

      
文件大?。?/td>
0K

      

      
描述：
IC FPGA PROASIC+ 600K 456-PBGA

      

      
標準包裝：
24

      

      
系列：
ProASICPLUS

      

      
RAM 位總計：
129024
      		

      

      
輸入/輸出數(shù)：
356
      		

      

      
門數(shù)：
600000
      		

      

      
電源電壓：
2.3 V ~ 2.7 V
      		

      

      
安裝類型：
表面貼裝
      		

      

      
工作溫度：
-40°C ~ 85°C
      		

      

      
封裝/外殼：
456-BBGA
      		

      

      
供應商設備封裝：
456-PBGA（35x35）
      		

      

      

      

	
      
    
    

    
      
	
      ProASICPLUS Flash Family FPGAs
      2- 6
      v5.9
      Input/Output Blocks
      To meet complex system demands, the ProASICPLUS
      family offers devices with a large number of user I/O
      pins; up to 712 on the APA1000. Table 2-3 shows the
      available supply voltage configurations (the PLL block
      uses an independent 2.5 V supply on the AVDD and
      AGND pins). All I/Os include ESD protection circuits. Each
      I/O has been tested to 2000 V to the human body model
      (per JESD22 (HBM)).
      Six or seven standard I/O pads are grouped with a GND
      pad and either a VDD (core power) or VDDP (I/O power)
      pad. Two reference bias signals circle the chip. One
      protects the cascaded output drivers, while the other
      creates a virtual VDD supply for the I/O ring.
      I/O pads are fully configurable to provide the maximum
      flexibility and speed. Each pad can be configured as an
      input, an output, a tristate driver, or a bidirectional
      buffer (Figure 2-6 and Table 2-4).
      Table 2-3 
      ProASICPLUS I/O Power Supply Voltages
      VDDP
      2.5 V
      3.3 V
      Input Compatibility
      2.5V
      3.3V
      Output Drive
      2.5V
      3.3V
      Figure 2-6  I/O Block Schematic Representation
      3.3 V / 2.5 V
      Signal Control
      Pull-up
      Control
      Pad
      Y
      EN
      A
      3.3 V / 2.5 V Signal Control Drive
      Strength and Slew-Rate Control
      Table 2-4 
      I/O Features
      Function
      Description
      I/O pads configured as inputs
      Selectable 2.5 V or 3.3 V threshold levels
      Optional pull-up resistor
      Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be
      configured as an input only, not a bidirectional buffer. This input type may be slower than
      a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros
      with an "S" in the standard I/O library have added Schmitt capabilities.
      3.3 V PCI Compliant (except Schmitt trigger inputs)
      I/O pads configured as outputs
      Selectable 2.5 V or 3.3 V compliant output signals
      2.5 V – JEDEC JESD 8-5
      3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)
      3.3 V PCI compliant
      Ability to drive LVTTL and LVCMOS levels
      Selectable drive strengths
      Selectable slew rates
      Tristate
      I/O pads configured as bidirectional
      buffers
      Selectable 2.5 V or 3.3 V compliant output signals
      2.5 V – JEDEC JESD 8-5
      3.3 V – JEDEC JESD 8-A (LVTTL and LVCMOS)
      3.3 V PCI compliant
      Optional pull-up resistor
      Selectable drive strengths
      Selectable slew rates
      Tristate
      
    
      
    
    
      


      


      

      相關PDF資料
      		

      PDF描述
      		

      
      

      
APA600-BGG456I
IC FPGA PROASIC+ 600K 456-PBGA

      

      
RMA50DRMD-S273
CONN EDGECARD 100POS .125 SQ WW

      

      
AX1000-2FG676
IC FPGA AXCELERATOR 1M 676-FBGA

      

      
AX1000-2FGG676
IC FPGA AXCELERATOR 1M 676-FBGA

      

      
ASM43DSEI-S13
CONN EDGECARD 86POS .156 EXTEND

      

      

      

      


      


      

      相關代理商/技術參數(shù)
      		

      參數(shù)描述
      		

      
      

      
APA600-BG456M
 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 600K Gates 180MHz 0.22um Technology 2.5V 456-Pin BGA 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 600K GATES 180MHZ 0.22UM 2.5V 456BGA - Trays

      

      
APA600-BGB
 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs

      

      
APA600-BGES
 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs

      

      
APA600-BGG456
功能描述:IC FPGA PROASIC+ 600K 456-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs
	Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）

      

      
APA600-BGG456I
功能描述:IC FPGA PROASIC+ 600K 456-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs
	Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）

      

      
    
    
    
	
      	
    
    
     
     
      發(fā)布緊急采購，3分鐘左右您將得到回復。
      
 
     
      

   	  
      
     

      
                    			    				      
      
                
      
                  
      
                    
                    
      
                      
      
                      
                      
      采購需求
        (若只采購一條型號，填寫一行即可)
      
                      
                      
      發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價
      
                      
                      
      發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價
      
                       
                        
      
                                
                                
      
                                    *型號
                                    *數(shù)量
                                    廠商
                                    批號
                                    封裝
                                  
      
                                      
                                
                                
      
                                    
                                        
      
                                            
                                            
                                        
      
                                          		
                                     
                                    
                                        
      
                                          		
                                    
                                        
      
                                          		
                                    
                                        
      
                                          		
                                    
                                        
      
                                          		
                                  
      
                                  
                                   
                                      
                            
      
                             
                             
							                            
      
                          添加更多采購
      
                      
      
                      
                      
      
                      
                      
      我的聯(lián)系方式
      
                     
                     
                       
      
                                
                                
                                
      
                                    
                                         *
                                    
                                    
                                  
      
                                  
                                  
      
                                    
                                         *
                                    
                                    
                                  
      
                                  
                                  
      
                                    
                                        
                                    
                                    
                                  
      
                                  
                                  
      
                                    
                                         *