
Copyright
ANPEC Electronics Corp.
Rev. A.
1 -
Apr
.,
2003
APA4838
www.anpec.com.tw
23
Table 1. Efficiency Vs Output Power in 5-V/8
BTL
Systems
Internal and External Gain Selection (Cont.)
At low frequencies C
LF
is a virtual open circuit and at
high frequencies, its nearly zero ohm impedance
shorts R
LF
. The result is increased bridge-amplifier
gain at low frequencies. The combination of R
LF
and
C
LF
form a -6dB corner frequency at
Application Descriptions ( Cont.)
Volume Adjustable and Fixed Gain selection
The APA4838 has an internal stereo volume control
whose setting is a function of the DC voltage applied
to the DC Vol control pin. The APA4838 volume con-
trol consists of 31 steps that are individually selected
by a variable DC voltage level on the DC Vol control
pin. The range of the steps, controlled by the DC
voltage, are from 0dB to -78dB. Each gain step cor-
responds to a specific input voltage range, as shown
in table. To minimize the effect of noise on the vol-
ume control pin, which can affect the selected gain
level, hysteresis and internal clock delay are
implemented. The amount of hysteresis corresponds
to half of the step width, as shown in volume control
graph.
For highest accuracy, the voltage shown in the ’rec-
ommended voltage’ column of the table is used to
select a desired gain. This recommended voltage is
exactly halfway between the two nearest transitions.
The gain levels are 1dB/step from 0dB to -6dB, 2dB/
step from -6dB to -52dB, and the last step at -78dB
as mute mode.
BTL Amplifier Efficiency
An easy-to-use equation to calculate efficiency starts
out as being equal to the ratio of power from the power
supply to the power delivered to the load. The fol-
lowing equations are the basis for calculating ampli-
fier efficiency.
Efficiency =P
SUP
(10)
P
O
Where :
Efficiency of a BTL configuration :
P
O
= V
RL
ORMS
x V
ORMS
2RL
V
P
xV
P
V
ORMS
=
√
2
P
SUP
= V
DD
x I
DDRMS
= V
DD
x2V
P
V
P
(11)
(12)
π
R
L
DD
x 2V
2R
L
P
O
P
SUP
=( ) / (V
P
xV
P
P
R
L
π
V
P
2V
DD
(13)
Table 1 calculates efficiencies for four different out-
put power levels when load is 8
.
Po (W) Efficiency (%) I
DD
(A)
V
PP
(V) P
D
(W)
0.2
26.67
0.15
2.00
0.55
0.50
41.67
0.24
2.83
0.7
1.00
58.82
0.34
4.00
0.7
1.3
68.42
0.38
4.47
0.6
**High peak voltages cause the THD to increase.