ProASICPLUS Flash Family FPGAs v5.9 2-7 Power-Up Sequencing Whi" />
參數(shù)資料
型號： APA450-FGG144
廠商： Microsemi SoC
文件頁數(shù)： 79/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 450K 144-FBGA
標準包裝： 160
系列： ProASICPLUS
RAM 位總計： 110592
輸入/輸出數(shù)： 100
門數(shù)： 450000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 144-LBGA
供應(yīng)商設(shè)備封裝： 144-FPBGA（13x13）
ProASICPLUS Flash Family FPGAs
v5.9
2-7
Power-Up Sequencing
While ProASICPLUS devices are live at power-up, the order
of VDD and VDDP power-up is important during system
start-up. VDD should be powered up simultaneously with
VDDP on ProASIC
PLUS devices. Failure to follow these
guidelines may result in undesirable pin behavior during
system start-up. For more information, refer to Actel’s
note.
LVPECL Input Pads
In addition to standard I/O pads and power pads,
ProASICPLUS devices have a single LVPECL input pad on
both the east and west sides of the device, along with
AVDD and AGND pins to power the PLL block. The
LVPECL pad cell consists of an input buffer (containing a
low voltage differential amplifier) and a signal and its
complement, PPECL (I/P) (PECLN) and NPECL (PECLREF).
The LVPECL input pad cell differs from the standard I/O
cell in that it is operated from VDD only.
Since it is exclusively an input, it requires no output
signal, output enable signal, or output configuration
bits. As a special high-speed differential input, it also
does not require pull-ups. Recommended termination
for LVPECL inputs is shown in Figure 2-7. The LVPECL pad
cell compares voltages on the PPECL (I/P) pad (as
illustrated in Figure 2-8) and the NPECL pad and sends
the results to the global MUX (Figure 2-11 on page 2-11).
This high-speed, low-skew output essentially controls the
clock conditioning circuit.
LVPECLs are designed to meet LVPECL JEDEC receiver
standard levels (Table 2-5).
Figure 2-7 Recommended Termination for LVPECL Inputs
Figure 2-8 LVPECL High and Low Threshold Values
Table 2-5
LVPECL Receiver Specifications
Symbol
Parameter
Minimum
Maximum
Units
VIH
Input High Voltage
1.49
2.72
V
VIL
Input Low Voltage
0.86
2.125
V
VID
Differential Input Voltage
0.3
VDD
V
+
_
PPECL
NPECL
From LVPECL Driver
Data
Z = 50
Ω
0
Z = 50
Ω
0
R = 100
Ω
2.72
2.125
1.49
0.86
Voltage
相關(guān)PDF資料
PDF描述
10326-32J0-006 JUNCTION SHELL 26POS BLACK
APA450-FG144 IC FPGA PROASIC+ 450K 144-FBGA
10326-32J0-003 JUNCTION SHELL 26POS GRAY
10368-32J0-006 JUNCTION SHELL 68POS GRAY
ABB40DHAR CONN EDGECARD 80POS R/A .050 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
APA450-FGG144A 功能描述:IC FPGA PROASIC+ 450K 144-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
APA450-FGG144I 功能描述:IC FPGA PROASIC+ 450K 144-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
APA450-FGG256 功能描述:IC FPGA PROASIC+ 450K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
APA450-FGG256A 功能描述:IC FPGA PROASIC+ 450K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
APA450-FGG256I 功能描述:IC FPGA PROASIC+ 450K 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*