ProASICPLUS Flash Family FPGAs 2- 38 v5.9 Table 2-24 DC" />
參數(shù)資料
型號: APA450-FG484
廠商: Microsemi SoC
文件頁數(shù): 122/178頁
文件大?。?/td> 0K
描述: IC FPGA PROASIC+ 450K 484-FBGA
標準包裝: 40
系列: ProASICPLUS
RAM 位總計: 110592
輸入/輸出數(shù): 344
門數(shù): 450000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 484-BGA
供應商設(shè)備封裝: 484-FPBGA(23x23)
ProASICPLUS Flash Family FPGAs
2- 38
v5.9
Table 2-24 DC Electrical Specifications (VDDP = 3.3 V ±0.3 V and VDD = 2.5 V ±0.2 V)
Applies to Military Temperature and MIL-STD-883B Temperature Only
Symbol
Parameter
Conditions
Military/MIL-STD-883B1
Units
Min.
Typ.
Max.
VOH
Output High Voltage
3.3 V I/O, High Drive, High Slew
(OB33PH)
3.3V I/O, High Drive, Normal/
Low Slew (OB33PN/OB33PL)
3.3 V I/O, Low Drive, High/
Normal/Low
Slew
(OB33LH/
OB33LN/OB33LL)
IOH = –8 mA
IOH = –16 mA
IOH = –3mA
IOH = –8mA
IOH = –3 mA
IOH = –8 mA
0.9
V
DDP
2.4
0.9
V
DDP
2.4
0.9
V
DDP
2.4
V
VOL
Output Low Voltage
3.3 V I/O, High Drive, High Slew
(OB33PH)
3.3V I/O, High Drive, Normal/
Low Slew (OB33PN/OB33PL))
3.3 V I/O, Low Drive, High/
Normal/Low
Slew
(OB33LH/
OB33LN/OB33LL)
IOL = 12 mA
IOL = 17 mA
IOL = 28 mA
IOL = 4 mA
IOL = 6 mA
IOL = 13 mA
IOL = 4 mA
IOL = 6 mA
IOL = 13 mA
0.1VDDP
0.4
0.7
0.1VDDP
0.4
0.7
0.1VDDP
0.4
0.7
V
VIH
2
Input High Voltage
3.3 V Schmitt Trigger Inputs
3.3 V LVTTL/LVCMOS
2.5 V Mode
1.6
2
1.7
VDDP + 0.3
V
VIL
3
Input Low Voltage
3.3 V Schmitt Trigger Inputs
3.3 V LVTTL/LVCMOS
2.5 V Mode
–0.3
0.7
0.8
0.7
V
RWEAKPULLUP Weak Pull-up Resistance
(IOB33U)
VIN 1.5 V
7
43
k
Ω
RWEAKPULLUP Weak Pull-up Resistance
(IOB25U)
VIN 1.5 V
7
43
k
Ω
IIN
Input Current
with pull up (VIN = GND)
–300
–40
A
without pull up (VIN = GND or VDD)
–10
10
A
IDDQ
Quiescent Supply Current
(standby)
Commercial
VIN = GND
4 or V
DD
Std.
5.015mA
IDDQ
Quiescent Supply Current
(standby)
Industrial
VIN = GND
4 or V
DD
Std.
5.0
20
mA
Notes:
1. All process conditions. Military Temperature / MIL-STD-883 Class B: Junction Temperature: –55 to +125°C.
2. During transitions, the input signal may overshoot to VDDP +1.0 V for a limited time of no larger than 10% of the duty cycle.
3. During transitions, the input signal may undershoot to –1.0 V for a limited time of no larger than 10% of the duty cycle.
4. No pull-up resistor required.
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