參數(shù)資料
型號： APA300-PQ208A
廠商： Microsemi SoC
文件頁數(shù)： 1/178頁
文件大?。?/td> 0K
描述： IC FPGA PROASIC+ 300K 208-PQFP
標準包裝： 24
系列： ProASICPLUS
RAM 位總計： 73728
輸入/輸出數(shù)： 158
門數(shù)： 300000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 208-BFQFP
供應商設(shè)備封裝： 208-PQFP（28x28）
December 2009
i
2009 Actel Corporation
See the Actel website for the latest version of the datasheet.
v5.9
ProASICPLUS Flash Family FPGAs
Features and Benefits
High Capacity
Commercial and Industrial
75,000 to 1 Million System Gates
27 K to 198 Kbits of Two-Port SRAM
66 to 712 User I/Os
Military
300, 000 to 1 Million System Gates
72 K to 198 Kbits of Two Port SRAM
158 to 712 User I/Os
Reprogrammable Flash Technology
0.22 m 4 LM Flash-Based CMOS Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Up Cycles
Mil/Aero Devices Operate over Full Military Temperature
Range
Performance
3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military
temperature)
Two Integrated PLLs
External System Performance up to 150 MHz
Secure Programming
The Industry’s Most Effective Security Key (FlashLock)
Low Power
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
High Performance Routing Hierarchy
Ultra-Fast Local and Long-Line Network
High-Speed Very Long-Line Network
High-Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
I/O
Schmitt-Trigger Option on Every Input
2.5 V / 3.3 V Support with Individually-Selectable Voltage
and Slew Rate
Bidirectional Global I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
Pin-Compatible Packages across the ProASICPLUS Family
Unique Clock Conditioning Circuitry
PLL
with
Flexible
Phase,
Multiply/Divide,
and
Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
Standard FPGA and ASIC Design Flow
Flexibility with Choice of Industry-Standard Front-End Tools
Efficient Design through Front-End Timing and Gate
Optimization
ISP Support
In-System Programming (ISP) via JTAG Port
SRAMs and FIFOs
SmartGen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
Table 1 ProASICPLUS Product Profile
Device
APA075
APA150
APA3001
APA450
APA6001
APA750
APA10001
Maximum System Gates
75,000
150,000
300,000
450,000
600,000
750,000
1,000,000
Tiles (Registers)
3,072
6,144
8,192
12,288
21,504
32,768
56,320
Embedded RAM Bits (k=1,024 bits)
27 k
36k
72 k
108 k
126 k
144 k
198 k
Embedded RAM Blocks (256x9)
12
16
32
48
56
64
88
LVPECL
222
2
PLL
222
2
Global Networks
4
Maximum Clocks
24
32
48
56
64
88
Maximum User I/Os
158
242
290
344
454
562
712
JTAG ISP
Yes
PCI
Yes
Package (by pin count)
TQFP
100, 144
100
–
PQFP
208
PBGA
–
456
FBGA
144
144, 256
144, 256, 484
256, 484, 676
676, 896
896, 1152
CQFP2
208, 352
CCGA/LGA2
624
Notes:
1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.
2. These packages are available only for Military/MIL-STD-883B devices.
v5.9
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
APA300-PQ208I 功能描述:IC FPGA PROASIC+ 300K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASICPLUS 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設(shè)備封裝:484-FPBGA（27X27）
APA300-PQ208M 制造商:Microsemi Corporation 功能描述:FPGA ProASICPLUS Family 300K Gates 180MHz 0.22um Technology 2.5V 208-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA PROASICPLUS 300K GATES 180MHZ 0.22UM 2.5V 208PQFP - Trays
APA300-PQ208MX319 制造商:Microsemi Corporation 功能描述:PROASICPLUS? 300K GATES 5MHZ MILITARY FLASH 2.5V 208 QFP - Trays
APA300-PQ896A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Automotive-Grade ProASIC Flash Family FPGAs
APA300-PQB 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs
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