- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4474 > APA150-TQ100I (Microsemi SoC)IC FPGA PROASIC+ 150K 100-TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | APA150-TQ100I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 103/178頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA PROASIC+ 150K 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ProASICPLUS |
| RAM 位總計(jì)： | 36864 |
| 輸入/輸出數(shù)： | 66 |
| 門數(shù)： | 150000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)當(dāng)前第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)
ProASICPLUS Flash Family FPGAs
2- 20
v5.9
User Security
ProASICPLUS devices have FlashLock protection bits that,
once
programmed,
block
the
entire
programmed
contents from being read externally. Refer to Table 2-11
for details on the number of bits in the key for each
device. If locked, the user can only reprogram the device
employing the user-defined security key. This protects
the device from being read back and duplicated. Since
programmed data is stored in nonvolatile memory cells
(actually very small capacitors) rather than in the wiring,
physical deconstruction cannot be used to compromise
data. This type of security breach is further discouraged
by the placement of the memory cells beneath the four
metal layers (whose removal cannot be accomplished
without disturbing the charge in the capacitor). This is
the highest security provided in the industry. For more
information,
refer
to
Actel’s
Nonvolatile Flash and Antifuse FPGAs white paper.
Embedded Memory Floorplan
The embedded memory is located across the top and
bottom of the device in 256x9 blocks (Figure 1-1 on page
1-2). Depending on the device, up to 88 blocks are
available to support a variety of memory configurations.
Each block can be programmed as an independent
memory array or combined (using dedicated memory
routing resources) to form larger, more complex memory
configurations. A single memory configuration could
include blocks from both the top and bottom memory
locations.
Embedded Memory Configurations
The embedded memory in the ProASICPLUS family
provides great configuration flexibility (Table 2-12). Each
ProASICPLUS block is designed and optimized as a two-
port memory (one read, one write). This provides 198
kbits of two-port and/or single port memory in the
APA1000 device.
Each memory block can be configured as FIFO or SRAM,
with
independent
selection
of
synchronous
or
asynchronous
read
and
write
ports
Additional characteristics include programmable flags as
well as parity checking and generation. Figure 2-18 on
page 2-22 and Figure 2-19 on page 2-23 show the block
diagrams of the basic SRAM and FIFO blocks. Table 2-14
on page 2-22 and Table 2-15 on page 2-23 describe
memory
block
SRAM
and
FIFO
interface
signals,
respectively. A single memory block is designed to
operate at up to 150 MHz (standard speed grade typical
conditions). Each block is comprised of 256 9-bit words
(one read port, one write port). The memory blocks may
be cascaded in width and/or depth to create the desired
memory organization. (Figure 2-20 on page 2-24). This
provides optimal bit widths of 9 (one block), 18, 36, and
72, and optimal depths of 256, 512, 768, and 1,024. Refer
to Actel’s SmartGen User’s Guide for more information.
Figure 2-21 on page 2-24 gives an example of optimal
memory usage. Ten blocks with 23,040 bits have been
used to generate three arrays of various widths and
depths. Figure 2-22 on page 2-24 shows how RAM blocks
can be used in parallel to create extra read ports. In this
example, using only 10 of the 88 available blocks of the
APA1000 yields an effective 6,912 bits of multiple port
RAM. The Actel SmartGen software facilitates building
wider and deeper memory configurations for optimal
memory usage.
Table 2-11 Flashlock Key Size by Device
Device
Key Size
APA075
79 bits
APA150
79 bits
APA300
79 bits
APA450
119 bits
APA600
167 bits
APA750
191 bits
APA1000
263 bits
Table 2-12 ProASICPLUS Memory Configurations by Device
Device
Bottom
Top
Maximum Width
Maximum Depth
DWDW
APA075
0
12
256
108
1,536
9
APA150
0
16
256
144
2,048
9
APA300
16
256
144
2,048
9
APA450
24
256
216
3,072
9
APA600
28
256
252
3,584
9
APA750
32
256
288
4,096
9
APA1000
44
256
396
5,632
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7130LA55J | IC SRAM 8KBIT 55NS 52PLCC |
| EP4CGX30CF19C8 | IC CYCLONE IV GX FPGA 30K 324FBG |
| IDT71V416L12PHGI | IC SRAM 4MBIT 12NS 44TSOP |
| AFS090-FG256I | IC FPGA 2MB FLASH 90K 256FBGA |
| AFS090-FGG256I | IC FPGA 2MB FLASH 90K 256FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| APA150-TQ896A | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Automotive-Grade ProASIC Flash Family FPGAs |
| APA150-TQB | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA150-TQES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA150-TQG100 | 功能描述:IC FPGA PROASIC+ 150K 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASICPLUS 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| APA150-TQG100A | 功能描述:IC FPGA PROASIC+ 150K 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASICPLUS 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。