參數(shù)資料
型號(hào): AP1086K25A
英文描述: 1.5A Low Dropout Positive Adjustable or Fixed-Mode Regulator
中文描述: 1.5A的低壓差正可調(diào)或固定模式穩(wěn)壓器
文件頁數(shù): 7/13頁
文件大?。?/td> 92K
代理商: AP1086K25A
ML4818
PRODUCT SPECIFICATION
7
REV. 1.0.3 6/21/01
The ML4818 can also be used in current mode by sensing
load current on the RAMP input (pin 3).
The four output delay timers are programmed via an external
R
resistor as shown below. This resistor value should be
no less than 1k
. Expressing R
DELAY
in k
the delay, in ns
is:
The ML4818 contains special logic circuits to provide for
voltage mode feed-forward and lock out long pulses into the
internal logic. This prevents instability from occuring when
the
Φ
Comparator trips in voltage mode.
Figure 3. Voltage Feed-Forward Circuit
The collector of Q
R
in figure 3 is high only during a power
cycle. When the power cycle terminates, RAMP is pulled
low. In voltage mode operation, a capacitor is connected
from RAMP to GND with a resistor from RAMP to V
IN
to
provide input voltage feed forward.
Oscillator
The ML4818 oscillator charges the external capacitor, C
T
,
with a current (I
SET
) equal to 5/R
T
. When the C
T
voltage
reaches the upper threshold (Ramp Peak), the comparator
changes state, turning on the current sink which discharges
C
T
to the lower threshold (Ramp Valley). The C
T
pin is
clamped to Ramp Valley by Q1 (Figure 5) to prevent inaccu-
racy due to undershoot on C
T
.
To use the CLOCK output for driving external synchroniza-
tion circuitry, a pull-down resistor is required from CLOCK
to GND.
Figure 4. Ocillator Timing Diagram
Figure 5. Ocillator Block Diagram
For frequencies of less than 500kHz, oscillator frequency
can be set by using the following formulae:
Error Ampli
fi
er
The ML4818 error amplifier is a 2.5MHz bandwidth, 8.5V/
μs slew rate op-amp with provision for limiting the positive
output voltage swing (output inhibit line) to implement the
soft start function. The error amplifier output source current
is limited to 4.5mA.
Figure 6. Error Amplifier Open-Loop Gain and Phase vs.
Frequency
Figure 7. Power Driver Simplified Schematic
T
DELAY
33
R
DELAY
×
=
45
+
(1)
3
RAMP
S
R
Q
Φ
MOD
OUTPUT
OSC
Q
R
CLOCK
T
D
C
T
RAMP PEAK
RAMP VALLEY
T
C
11
+
2
13
5V
CLOCK
OUT
5V
5.5mA
1.7V
R
T
I
SET
C
T
I
SET
250
Q1
f
OSC
T
T
T
+
--------------------------------------------------
=
(2)
120
100
80
60
40
20
0
180
135
90
45
0
0
100
1k
10k
100k
1M
10M
FREQUENCY
G
P
GAIN
PHASE
POWER
GND
Q1
Q2
OUT
V
CC
V
CC
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