參數(shù)資料
型號: AOZ1017
廠商: ALPHA
英文描述: EZBuck⑩ 3A Simple Regulator
中文描述: EZBuck⑩3A條簡單的穩(wěn)壓
文件頁數(shù): 12/16頁
文件大小: 612K
代理商: AOZ1017
AOZ1017
Rev. 1.0 July 2007
www.aosmd.com
Page 12 of 16
SO-8
1
2
3
4
8
7
6
5
PGND
AGND
COMP
LX
LX
EN
FB
Cout
CC
RC
L
VIN
Cin
The maximum junction temperature of AOZ1017 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1017 under different ambient
temperatures.
The thermal performance of the AOZ1017 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
Several layout tips are listed below for the best electric
and thermal performance. Figure 3 illustrates a PCB
layout example as reference.
1.
Do not use thermal relief connection to the V
IN
and
the PGND pin.
M
aximize
the
copper area
for
the
PGND pin and the V
IN
pin to help thermal dissipation.
Input capacitor should be connected as close as
possible to the V
IN
pin and the PGND pin.
2.
3.
A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
4.
Make the current trace from LX pins to L to C
O
to the
PGND as short as possible.
5.
Pour copper plane on all unused board area and
connect it to stable DC nodes, like V
IN
, GND or V
OUT
.
The two LX pins are connected to the internal PFET
drain. They are low resistance thermal conduction
path and most noisy switching node. Connecting a
copper plane to the LX pins will help thermal
dissipation. This copper plane should not be too
larger otherwise switching noise may be coupled to
other part of circuit.
6.
7.
Keep sensitive signal trace
s
away from the LX pins.
Figure 3. AOZ1017 PCB Layout
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