參數(shù)資料
型號(hào): AOZ1015
廠商: ALPHA
英文描述: EZBuck⑩ 1.5A Synchronous Buck Regulator
中文描述: EZBuck⑩1.5A的同步降壓穩(wěn)壓器
文件頁(yè)數(shù): 11/15頁(yè)
文件大?。?/td> 715K
代理商: AOZ1015
AOZ1015
Rev. 1.2 September 2007
www.aosmd.com
Page 11 of 15
The previous equation above can also be simplified to:
×
----------------------
=
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at
www.aosmd.com
.
Thermal Management and Layout
Consideration
In the AOZ1015 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the V
IN
pin, to the
LX pins, to the filter inductor, to the output capacitor
and load, and then returns to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the PGND pin of the
AOZ1015, to the LX pins of the AOZ1015. Current flows
in the second loop when the low side diode is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is recommended to connect input capacitor, output
capacitor, and PGND pin of the AOZ1015.
In the AOZ1015 buck regulator circuit, the two major
power dissipating components are the AOZ1015 and
the output inductor. The total power dissipation of
converter circuit can be measured by input power minus
output power.
The power dissipation of the inductor can be approxi-
mately calculated by output current and DCR of inductor.
The actual AOZ1015 junction temperature can be
calculated with power dissipation in the AOZ1015 and
thermal impedance from junction to ambient.
The maximum junction temperature of the AOZ1015 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for the maximum
load current of the AOZ1015 under different ambient
temperatures.
The thermal performance of the AOZ1015 is strongly
affected by the PCB layout. Extra care should be taken
by users during the design process to ensure that the IC
will operate under the recommended environmental
conditions.
Several layout tips are listed below for the best electronic
and thermal performance. Figure 3 illustrates a single
layer PCB layout example as reference.
1.
Do not use thermal relief connection to the V
IN
and
the PGND pins. Pour a maximized copper area to the
PGND pin and the V
IN
pin to help thermal dissipation.
The input capacitors should be connected as close
as possible to the V
IN
and PGND pins.
A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin. In this case, a decoupling
capacitor should be connected between V
IN
and
AGND.
2.
3.
4.
Make the current trace from LX pins to L to C
O
to the
PGND as short as possible.
5.
Pour copper plane on all unused board area and
connect it to stable DC nodes, like V
IN
, GND or V
OUT
.
The two LX pins are connected to the internal PFET
drain. They are low resistance thermal conduction
path and a noisy switching node. Connecting a
copper plane to the LX pin to help thermal dissipa-
tion. This copper plane should not be too large
otherwise switching noise may be coupled to other
parts of the circuit.
6.
7.
Keep sensitive signal traces such as trace
connecting FB and COMP away from the LX pins.
C
C
C
R
L
R
C
P
total_loss
V
IN
I
IN
V
O
I
O
×
×
=
P
inductor_loss
I
O
2
R
inductor
1.1
×
×
=
T
junction
P
total_loss
P
inductor_loss
T
ambient
+
(
)
Θ
×
=
+
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