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參數(shù)資料
| 型號： | AN8049FHN |
| 廠商： | PANASONIC CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 1.8-volt 3-channel step-up, step-down, and polarity inverting DC-DC converter control IC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC24 |
| 封裝： | 4 X 5 MM, PLASTIC, QFN-24 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大小： | 170K |
| 代理商： | AN8049FHN |
Voltage Regulators
AN8049FHN
11
I
Usage Notes
[1] Allowable power dissipation
Since the power dissipation (P) in this IC increases proportionally with the supply voltage, applications must be
careful to operate so that the loss does not exceed the allowable power dissipation, P
D
, for the package.
Reference formula:
P = (V
CC
V
BEQ1
)
×
I
SO(OUT)1
×
Du
1
←
Power dissipation in the channel 1 output stage
+
(V
CC
V
BEQ2
)
×
I
SO(OUT)2
×
Du
2
←
Power dissipation in the channel 2 output stage
+
V
O(SAT)3
×
I
OUT3
×
Du
3
←
Power dissipation in the channel 3 output stage
+
V
CC
×
I
CC
←
Power dissipation between V
CC
and ground
<
P
D
V
BEQ1
:
The voltage between the base and emitter of the npn transistor Q1
I
SO(OUT)1
: The OUT1 pin output source current
(When R
RB1
is 1 k
, I
SO(OUT)1
will be 38 mA, maximum.)
Du
1
: The output 1 duty factor
V
BEQ2
: The voltage between the base and emitter of the npn transistor Q2
I
SO(OUT)2
: The OUT2 pin output source current
(When R
RB2
is 1 k
, I
SO(OUT)2
will be 38 mA, maximum.)
Du
2
: The output 2 duty factor
V
O(SAT)3
: The OUT3 pin saturation voltage (0.5 V maximum when OUT1 is 40 mA.)
I
OUT3
: The OUT3 pin current (This will be {V
CC
V
BEQ3
V
O(SAT)3
}/R
O3
.)
Du
3
: The output 3 duty factor
I
CC
: The V
CC
pin current
[2] Allowable V
CC
ripple
V
CC
ripple due to the switching transistor being turned on and off can cause this IC's U.V.L.O. circuit, which is
biased by V
CC
, to operate incorrectly, and can cause the S.C.P. capacitor charging operation to fail to start when the
output is shorted.
The figure shows the allowable range for V
CC
ripple. Applications should reduce V
CC
ripple to be within this range,
either by inserting a ripple filter in the V
CC
line or by inserting a capacitor between the IC GND and V
CC
pins and
locating that capacitor as close to the IC as possible.
Note that the allowable range shown here is the result of testing the IC alone and that the allowable range may
differ depending on the actual structure of the power supply circuit. Also note that this allowable range is a design
target, and is not guaranteed by testing of all samples.
Allowable V
CC
ripple
R
10 M
1 M
100 k
10 k
V
CC
ripple voltage V
CC
(AC) (V[p-p])
0
1
2
3
4
5
6
7
8
Allowable range
when V
CC
is 3 V.
Allowable range
when V
CC
is 10 V.
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