參數(shù)資料
型號： AN5693K
廠商： PANASONIC CORP
元件分類： 消費(fèi)家電
英文描述： Luminance,Chroma and Sync. Signals Processing ICwith Built-in I2Cbus Interfacefor PAL/NTSC Color-TV
中文描述： SPECIALTY CONSUMER CIRCUIT, PDIP52
封裝： 0.600 INCH, PLASTIC, SDIP-52
文件頁數(shù)： 30/34頁
文件大?。?/td> 325K
代理商： AN5693K
30
AN5693K
ICs for TV
I
Technical Data (continued)
Outline of major blocks (continued)
RGB
(1) OSD is made up of 3 colors of RGB, by using simple analog input, of which input at 0 V is fixed at the
pedestal level.(The input dynamic range is controllable by contrast)
(2) White balance(drive, cutoff)adjustment is implemented by I
2
C bus.
(3) Spot killer is built-in : When power supply is off, R, G, B, output levels increase, the residue spot that is
visible on the CRT is eliminated.
Jungle
(1) 2-pin are used for synchronous inputs(Horizontal, Vertical)to improve the synchronisation characteristics of
horizontal and vertical synchronisation.
(2) The horizontal circuit is based on countdown method using a 32 f
H
ceramic oscillator.
AFC circuit is employing the doubler method.
(3) The vertical circuit is employing the trigger method's countdown circuit, thereby resulting in no adjustment
and stable vertical synchronisation. The pulse output will not be interfered by interlace which is caused by
pattern layout.
(4) Vertical frequency identification circuit is built-in : the output of 50/60 Hz identification is determined
according to the vertical synchronous frequency.(60 Hz
→
"H")
Below 45 Hz and above 65 Hz, the previous state is hold. After 3 consecutive vertical period, if 60 or 50 Hz
is identifield, the initial output will be changed.
45
Input frequency
Hold
Idetification
output voltage
(5) Horizontal lock detection circuit and X-ray protection circuit(Shut down method)are built-in.
(6) Picture centre position is adjustable by I
2
C bus.(
±
1.6
μ
s)
(7) In the case of blue back in a weak field, the vertical trigger can be in off mode(I
2
C bus).
Thus a stable picture is maintained.
50Hz
(Low)
60Hz
(High)
55
65
Hold
I
2
C Bus
(1) There are 15 built-in DAC controls and 13 built-in switches to reduce adjustment for set maker.
(2) Auto-increment function present :
Sub address 0*: Auto-increment mode
(When the data is sent in consecutive order, the sub-address will be changed in consecutive order, as data is
inputed)
Sub address 8*: Data refresh mode
(When the data is sent consecutively, it is sent to the same sub-address)
(3) I
2
C Bus Protocol
Slave address : 10001010(8AH)
Format(Usual)
S
Start
condition
Auto-increment mode/Data refresh mode
0
A
A
A
P
Sub address
Slave address
Data byte
S
0
A
A
A
A
P
Sub address
Slave address
Data 1
A
Data 2
Data n
Stop
condition
Write Acknowledge bit
(4) Because DAC initial condition is not guaranteed, during power on, it is necessary to input the required standard data.
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