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參數(shù)資料
| 型號： | AN5392FBQ |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Luminance and color difference drive/cutoff signal processor IC with I2C bus |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 14 X 14 MM, PLASTIC, QFS-64 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 206K |
| 代理商： | AN5392FBQ |
AN5392FBQ
ICs for TV
20
Pin No.
Equivalent circuit
Description
52
Y (S) in:
Sub signal Y input pin
Input 0.7 V[0-p] (B-W) for both HD and
NTSC.
Drive this pin with a low impedance. High
impedance is likely to cause variation of
white balance with the user volume.
Clamps the input signal with the clamp pulse
of the following pins:
Pin 56, I
2
C bus M1/M2 switch: M1
Pin 60, I
2
C bus M1/M2 switch: M2
Recommended use range:
Do not apply DC voltage from outside
53
Refer to pin 51
Refer to pin 51
54
Refer to pin 10
Refer to pin 10
55
M/S in:
M/S (main/sub) switching signal input pin
Input threshold voltage: 1.5 V
1) 2.1 V
<
V
55
Outputs the signal inputted from M1 or
M2.
2) V
55
<
0.9 V
Outputs the signal inputted from M1 or
M2.
Note) If you switch over a multi-screen in a high
speed within 1H period, WB will be changed.
Be careful on use. The degree of WB changes
depending upon the setting of DAC.
Priority order of signal switching over
M1/M2 (I
2
C SW)
<
M/S
<
Y
M
<
Y
S
Recommended use range: 0 V to 5 V
56
CLP (M1) in:
Main signal (M1) signal clamp pulse input pin
Input threshold voltage: 1.5 V
(clamps at high)
Clamps the signal inputted from the next pin
Pin 57, pin 58, pin 59
Recommended clamp pulse width
NTSC: 2.5
μ
s, HD: 1.0
μ
s
Recommended use range: 0 V to 5 V
I
Terminal Equivalent Circuits (continued)
1 k
1 k
400
μ
A
40
μ
A
3.75 V
V
CC
9 V (Y,U,V V
CC
/pin 54)
200
52
0.7 V[0-p]
4.5 V
NP, 1
μ
F
5 V
0 V
V
CC
9 V (Y,U,V V
CC
/pin 54)
40
μ
A
40
μ
A
200
55
2.25 V
5 V
0 V
V
CC
9 V (Y,U,V V
CC
/pin 54)
40
μ
A
40
μ
A
200
56
2.25 V
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