參數(shù)資料
型號: AN5192K
廠商: PANASONIC CORP
元件分類: 消費(fèi)家電
英文描述: LJT 100C 100#22D PIN RECP
中文描述: SPECIALTY CONSUMER CIRCUIT, PDIP64
封裝: 0.750 INCH, PLASTIC, SDIP-64
文件頁數(shù): 13/23頁
文件大小: 221K
代理商: AN5192K
ICs for TV
AN5192K
13
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Color signal processing circuit (continued)
(Burst 300 mV[p-p] (PAL), reference is B-out)
Brightness variation with color
V
BC
Pedestal level DC difference
between at contrast max. and min.
250
0
250
mV
Brightness variation difference
voltage with color
V
BC
R, G, B out variation voltage
difference
0
20
mV
RGB processing circuit
(C-Y)/Y
R
C/Y
Color bar input, B-out
Contrast typ., color Data 00
=
60
0.9
1.2
1.5
V[0-p]/
V[p-p]
(C-Y), Y delay difference
T
C/Y
Color bar input, B-out
Phase of green
magenta
100
0
100
ns
Y
S
changeover speed
f
YS
f
YS,
when external input is 3 V,
output level
3 dB
7
11
MHz
External RGB input dynamic
range
V
DEXT
Contrast max., Data 03
=
77F
2.0
2.5
3.2
V[0-p]
Internal/external crosstalk
CT
RGB
Leakage when f
=
1 MHz, 1 V[p-p],
and Y
S
=
5 V
60
50
dB
Spot killer operation
V
SPK
V
9,
when V
9
is
decreased from 9 V
and spot killer turns on.
7.4
7.8
8.2
V
Brightness variation with contrast
V
BAC
Pedestal level DC difference between
contrast max. and min.
250
0
250
mV
Brightness variation difference
voltage with contrast
V
BAC
R, G, B out variation voltage
difference
0
20
mV
Pedestal level fluctuation with V
CC
V
PL/V
V
CC1
=
9 V (allowance:
±
10%)
0
200
400
mV/V
Pedestal level- temperature
characteristics
V
PL/T
T
a
=
20
°
C to
+
70
°
C
2.6
2.2
1.8
mV/
°
C
Pedestal level 2
V
PD2
Pedestal level, when G cutoff
Data 05
=
18
2.1
2.7
3.3
V
Synchronizing signal processing circuit
Lock detection output voltage
V
LD
V
18
at horizontal AFC lock
5.7
6.3
6.9
V
Lock detection charge and discharge current
EBP (RGB) slice level
I
LD
V
FBP
DC measurement
Minimum voltage of pin 50, when
blanking is applied to RGB output
±
0.6
0.4
±
0.8
0.75
±
1.1
1.1
mA
V
EBP (AFC2) slice level
V
FBPH
Minimum voltage of pin 50 at which
AFC2 operates
1.5
1.9
2.3
V
Horizontal AFC
μ
μ
H
DC measurement
30
37
44
μ
A/
μ
s
Horizontal VCO
β
β
H
β
curve gradient near f
=
15.7kHz
1.4
1.9
2.4
Hz/mV
Burst gate pulse position
P
BGP
For both PAL/NTSC, delay from
H. Sync. rise
0.2
0.4
0.6
μ
s
I
Electrical Characteristics at T
a
=
25
°
C (continued)
Design reference data (continued)
Note) The characteristic listed below are theoretical values based on the IC design and are not guaranteed.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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