參數(shù)資料
型號: AN5165K
廠商: PANASONIC CORP
元件分類: 消費(fèi)家電
英文描述: A Single Chip IC for NTSC Color-TV
中文描述: SPECIALTY CONSUMER CIRCUIT, PDIP52
封裝: 0.600 INCH, PLASTIC, SDIP-52
文件頁數(shù): 13/24頁
文件大小: 275K
代理商: AN5165K
13
ICs for TV
AN5165K
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Synchronizing signal processing circuit
Horizontal output start voltage
V
fHS
Minimum V
46
, when H osc. output is
1 V[p-p] or more and f
O
becomes
>
10 kHz
3.9
4.4
4.9
V
Lock detection output voltage 1
V
LD1
V
11
, when horizontal AFC is locked
3.8
4.3
4.8
V
Lock detection output voltage 2
V
LD2
V
11
, when horizontal AFC is unlocked.
0
0.1
0.5
V
Lock detection charge and discharge
current
I
LD
DC measurement
±
0.5
±
0.7
±
1.1
mA
EBP (BLK) slice level
V
FBP
Minimum voltage of pin 45, when
blanking is applied to RGB output
0.3
0.66
1.0
V
EBP (AFC2) slice level
V
FBPH
Minimum voltage of pin 45, when
AFC2 operates
1.45
1.85
2.25
V
Horizontal AFC
μ
μ
H
DC measurement
26
33
40
μ
A/
μ
s
Horizontal VCO
β
β
H
β
curve gradient near f
=
15.75 kHz
1.4
1.8
2.2
Hz/mV
Burst gate pulse position
P
BGP
Delay from H
SYNC
rise
0.2
0.4
0.6
μ
s
Burst gate pulse width
W
BGPN
2.5
3.0
3.5
μ
s
V blanking pulse width
W
VN
Pulse width, when f
H
=
15.75 kHz
1.04
1.14
1.24
ms
EBP allowable range
T
FBP
Time from H
OUT
rise to FBP center
12
19
μ
s
Overvoltage protective operation
voltage
V
XRAY
Dispersion from the minimum voltage
at which H osc. comes to be out of
synchronization
60
60
mV
Black-out operation voltage
V
BLOUT
Difference voltage from hold-down
to black out
10
110
160
mV
H
SYNC2
output level
V
SCP
H
SYNC2
output DC level
8.0
8.2
8.4
V
H
SYNC2
output width
W
SCP
H
SYNC2
output pulse width
2
μ
s
H
SYNC2
output position
P
SCP
The period of time from H
SYNC
center to H
SYNC2
rise
3
μ
s
Horizontal output pulse duty cycle
t
HO
Upward going pulse duty cycle
32
38
44
%
Horizontal output voltage (high)
V
50H
High level DC voltage
2.8
3.1
3.4
V
Horizontal output voltage (low)
V
50L
Low level DC voltage
0
0.3
V
Vertical output voltage (high)
V
52H
High level DC voltage
3.9
4.2
4.5
V
Vertical output voltage (low)
V
52L
Low level DC voltage
0
0.3
V
Synchronizing signal clamp voltage (Ver.)
V
39
V
39
clamp voltage
3.2
3.6
4.0
V
Synchronizing signal clamp voltage (Hor.)
V
41
V
41
clamp voltage
3.2
3.6
4.0
V
External blanking input threshold level
V
16I
0.4
0.75
1.1
V
Vertical pull-in range
f
VP-N
f
H
=
15.75 kHz
56
64
Hz
I
Electrical Characteristics at T
a
=
25
°
C (continued)
Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
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