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參數(shù)資料
| 型號： | AN5095K |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Circular Connector; No. of Contacts:66; Series:MS27656; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:19; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP64 |
| 封裝： | 0.750 INCH, PLASTIC, SDIP-64 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 405K |
| 代理商： | AN5095K |
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14
AN5095K
ICs for TV
I
Electrical Characteristics at T
a
=
25
°
C (continued)
Design reference data (continued)
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Synchronizing signal processing circuit (continued)
FBR (R, G, B) slice level
V
FBP
Pin 50 minimum voltage at which
blanking is applied to R, G, B output
0.4
0.75
1.1
V
FBP (AFC2) slice level
V
FBPH
Pin 50 minimum voltage in which
AFC2 operates
1.5
1.9
2.3
V
Horizontal AFC
μ
Horizontal VCO
β
Burst gate pulse position
*8
μ
H
β
H
P
BGP
DC measurement
30
37
44
μ
A/
μ
s
β
curve slant near f
=
15.75 kHz
1.4
1.9
2.4
Hz/mV
Delay from H sync. rise for both PAL/
NTSC
0.2
0.4
0.6
μ
s
PAL burst gate pulse width
*8
W
BGPP
3.4
4.0
4.6
μ
s
μ
s
NTSC burst gate pulse width
*8
W
BGPN
2.5
3.0
3.5
Burst gate pulse output voltage
V
BGP
V
HBLK
Pin 62 DC voltage during BGP period
4.5
4.7
4.9
V
H blanking pulse output voltage
Pin62 DC voltage during H blanking
pulse period
2.1
2.4
2.7
V
V blanking pulse output voltage
V
VBLK
Pin62 DC voltage during V blanking
pulse period
2.1
2.4
2.7
V
PAL V blanking pulse width
W
VP
Pulse width at f
=
15.625 kHz
Pulse width at f
=
15.73 kHz
1.31
1.41
1.51
ms
NTSC V blanking pulse width
W
VN
1.01
1.11
1.21
ms
FBP allowable range
*9
T
FBP
V
AFBP
Time from H-out rise to FBP center
12
19
μ
s
FBP maximum allowable input
voltage
2.5
5.0
V
I
2
C interface
Bus free before start
t
BUF
4.0
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
Start condition set-up time
t
SU, STA
4.0
Start condition hold time
t
HD, STA
4.0
Low period SCL, SDA
t
LOW
4.0
High period SCL
t
HIGH
4.0
Rise time SCL, SDA
t
r
1.0
Fall time SCL, SDA
t
f
0.35
Data set-up time (write)
t
SU, DAT
0.25
Data hold time (write)
t
HD, DAT
0
Acknowledge set-up time
t
SU, ACK
3.5
Acknowledge hold time
t
HD, ACK
0
Stop condition set-up time
t
SU, STO
4.0
Note)*1 to *9: Refer to "Explanation of test methods".
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