- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364678 > AN2528 (飛思卡爾半導(dǎo)體(中國)有限公司) Standard Space Vector Modulation TPU Function Set (svmStd) PDF資料下載
參數(shù)資料
| 型號： | AN2528 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Standard Space Vector Modulation TPU Function Set (svmStd) |
| 中文描述： | 空間矢量調(diào)制標(biāo)準(zhǔn)聚氨酯函數(shù)集（svmStd） |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 514K |
| 代理商： | AN2528 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AN2528/D
14
Standard Space Vector Modulation TPU Function Set (svmStd)
For More Information On This Product,
Go to: www.freescale.com
10 IMB clock cycles. The service starts immediately after the top channel high
to low transition, which occurs at a period of
DT
before the bottom channel low
to high transition (see
Figure 6
), so that the latency is 28 IMB clock cycles + 10
IMB clock cycles –
DT
. The svmStd functions are designed so that no other
svmStd state can request service at this time. The
MPW
, in the case when only
svmStd functions are running on one TPU, is then
latency + 16 IMB clock cycles =
= 28 IMB clock cycles + 10 IMB clock cycles –
DT +
16 IMB clock cycles =
= 54 IMB clock cycles –
DT
and is a minimum at least 16 IMB clock cycles (when latency = 0).
Note that the
MPW
, as well as the
DT
, are not entered into the parameter RAM
in IMB clock cycles, but in TCR1 clock cycles. It is recommended for the
svmStd function that the TCR1 clck is configured for its maximum speed, which
is the IMB clock divided by 2. In this case the
MPW
= 27 –
DT
, with a minimum
value of 8.
When other functions are running together on the same TPU as the svmStd
functions, the latency could be lengthened. To maintain sufficiently high
performance of svmStd, it is recommended that the following rules are followed
to configure the TPU:
assign svmStd PWM channels high priority
assign svmStd PWM functions on low channel numbers so that no other
function with high priority is assigned a channel with a lower number
In this instance, one of the two worst case timing cases can happen. These are
illustrated in
Figure 7
and
Figure 8
. Which case occurs depends on the
DT
.
Figure 7. Worst case timing – case one
HL
LH_C5
bottom channel
top channel
MPW
latency
DT
H
TST+4
L
H
H
M
TST+4
TST
TST
TST
time slot sequence
F
Freescale Semiconductor, Inc.
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AN2528D | Standard Space Vector Modulation TPU Function Set (svmStd) |
| AN2701 | PWM Generation with the HC08 Timer |
| AN2821 | eTPU Host Interface |
| AN2848 | Programming the eTPU |
| AN2897 | Using the eTPU Angle Clock |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AN25-28 | 制造商: 功能描述: |
| AN2528D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Standard Space Vector Modulation TPU Function Set (svmStd) |
| AN2531 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Standard Space Vector Modulation with Dead-Time Correction ?XOR version TPU Function Set |
| AN2531/D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Standard Space Vector Modulation with Dead-Time Correction ?XOR version TPU Function Set |
| AN2532 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Standard Space Vector Modulation ? 3 outputs version TPU Function Set (svmStd3) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。