參數(shù)資料
型號(hào)： AN2407
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Reed Solomon Encoder/Decoder on the StarCore SC140/SC1400 Cores, With Extended Examples
中文描述： 里德所羅門編碼器/的StarCore SC140/SC1400核心解碼器，以擴(kuò)展實(shí)例
文件頁(yè)數(shù)： 11/48頁(yè)
文件大?。?/td> 306K
代理商： AN2407
SC140 Core Overview
Reed Solomon Encoder/Decoder on the StarCore SC140/SC1400 Cores, With Extended Examples, Rev. 1
Freescale Semiconductor
11
Figure 5.
SC140 Core
The SC140 core provides the following main functional units:
Data-arithmetic and logic unit (DALU) that includes four data-arithmetic and logic units (ALU) and a
bank of sixteen 40-bit registers, d0 to 15.
Address-generation unit (AGU):
— :Sixteen 32-bit address read/write registers, r0 to r15. The contents of an address register can either
point directly to data or function as an index.
— Two AAUs, each of which can update one address register during one instruction cycle.
Program sequencer and controller (PSEQ).
Memory interface:
— A 32-bit program memory address bus (PAB) and a 128-bit program memory data bus (PDB).
— Two data memory buses (32-bit address and 64-bit data bus pairs: XABA and XDBA, XABB, and
XDBB).
The SC140 core uses a unified memory space. Each address can contain either program information or data. There
are no separate memory spaces for program locations and data locations. The memory is made up of a number of
32 KB groups, and each group includes eight 4 KB modules. Memory contention, which causes a one-cycle stall,
can arise if two data accesses are to two different rows in the same memory module. The instruction set supports
various types of move instructions that differ in access width (byte, word, long word, two long words), data type
(signed, unsigned) and multiple-register moves. Integer moves from memory (byte, word, long, two long) are right
aligned in the destination register, and by default are sign-extended to the left. Unsigned moves are marked with
X
X
Instruction Bus
P
Program
Sequencer
P
X
X
2 AAUs
4 ALUs
Data ALU
Register File
Unified
128
64
64
32
32
32
128
128
BMU
24
Data/Program Memory
Management
Clock
Generator
PLL
Address Generator
Register File
Power
EOnCE
Instruction Set
Accelerator
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