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| 型號： | AN1812 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Freescale Semiconductor, Inc. |
| 中文描述： | Freescale半導體公司 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 465K |
| 代理商： | AN1812 |
MOTOROLA
Common Footprint for the MPC750, MPC755, MPC7400, and MPC7410
For More Information On This Product,
Go to: www.freescale.com
3
I/O Voltage Selection
1.2
I/O Voltage Selection
This section lists the four footprint power planes and displays the section matrix for the I/O voltages.
In addition, the footprint should have four power planes:
Ground
The CPU core voltage, [VDD]
The I/O voltage for the system bus, [OVDD]
The I/O voltage for the L2 SRAM interface, [L2OVDD]
The I/O voltages [OVDD and L2OVDD] are selectable on all the CPUs except the MPC750,
which supports 3.3V only on both of these interfaces.
Table 2 and Table 3 show the selection matrix for the I/O voltages:
G1
Input
DBDIS
DBDIS
No Function
DTI[2]
2
Pull-up to OVDD
1
A3
Input
TLBISYNC
TLBISYNC
EMODE
EMODE
Pull-up to OVDD (64-bit 60x
bus)
W1
No Connect
BVSEL
BVSEL
BVSEL
See Table 2 and Table 3 for
voltages.
A19
No Connect
L2VSEL
L2VSEL
L2VSEL
1
2
See the individual hardware speci
fi
cations document for the recommended resistor value.
DTI[0:2] should be pulled low in MPX bus mode to disable re-ordering.
Table 2. I/O Voltage Selection—BVSEL
BVSEL
MPC750
MPC755
MPC7400
MPC7410 (Rev E)
0
N/A
N/A
1.8V
1.8V
HRESET
N/A
N/A
N/A
2.5V
1
N/A
OVDD (2.5V/3.3V)
3.3V
3.3V
HRESET
N/A
N/A
N/A
3.3V
Unconnected
(internal pull-up)
N/A
2.5V/3.3V
3.3V
3.3V
Table 1. Main Pin Difference and Configuration Pins (continued)
Pin #
Type
MPC750
MPC755
MPC7400/
MPC7410
60x Bus
MPC7400/
MPC7410
MPX Bus
Comment
F
Freescale Semiconductor, Inc.
n
.
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