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參數(shù)資料
| 型號： | AN165 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EMI REDUCTION TECHNIQUES |
| 中文描述： | 電磁干擾抑制技術(shù) |
| 文件頁數(shù)： | 2/3頁 |
| 文件大?。?/td> | 38K |
| 代理商： | AN165 |
AN165
2
AN165REV1
4. PCB LAYOUT CHECKLIST
Connect analog and digital ground together
with a 1/16 inch trace under the CS4297A. A
direct connection between analog and digital
ground will reduce the differential-mode radia-
tion and improve the EOS (Electrical Over-
stress) capabilities of the CS4297A.
Construct a "clean" chassis ground on the PCB
around the I/O connectors, and connect the I/O
ground to the system frame ground.
Connect chassis ground to digital ground in a
quiet area, away from the CS4297A.
The ferrite bead and decoupling capacitor com-
bination shown in the block diagram on page
one of this document, form a low-pass filter to
remove the common-mode voltages. The de-
coupling capacitor must be terminated to a
clean (free of digital noise) I/O chassis ground.
A separate analog ground return path between
the I/O connectors and analog ground plane
must be maintained to reduce loop areas.
Chassis and analog planes should be identical
on all layers, and the gap or "moat" between
planes should be 1/8 inch to prevent coupling
between planes. The absolute minimum moat
spacing is 1/16 inch. Do not overlap digital and
analog ground planes.
Never route digital traces or digital planes un-
der the analog or I/O chassis ground areas. An-
alog components should be located over analog
planes and digital components should be locat-
ed over digital planes.
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provid
ed “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
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