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參數(shù)資料
| 型號(hào)： | AMIS30660CANH6RG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSCEIVER CAN HS 5V 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | CAN |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 帶卷 (TR) |
AMIS30660
http://onsemi.com
6
Table 6. DC AND TIMING CHARACTERISTICS
(VCC = 4.75 V to 5.25 V; Tjunc = 40°C to +150°C; RLT = 60 W unless specified otherwise.)
Symbol
Unit
Max
Typ
Min
Conditions
Parameter
BUS LINES (Pins CANH and CANL)
Vi(dif)(th)
Differential receiver threshold voltage
5 V < VCANL < +10 V;
5 V < VCANH < +10 V;
See Figure 4
0.5
0.7
0.9
V
Vihcm(dif) (th)
Differential receiver threshold voltage for
high commonmode
35 V < VCANL < +35 V;
35 V < VCANH < +35V;
See Figure 4
0.25
0.7
1.05
V
Vi(dif) (hys)
Differential receiver input voltage hyster-
esis
5 V < VCANL < +10 V;
5 V < VCANH < +10 V;
See Figure 4
50
70
100
mV
Ri(cm)(CANH)
Commonmode input resistance at pin
CANH
15
25
37
KW
Ri(cm) (CANL)
Commonmode input resistance at pin
CANL
15
25
37
KW
Ri(cm)(m)
Matching between pin CANH and pin
CANL commonmode input resistance
VCANH = VCANL
3
0
+3
%
Ri(dif)
Differential input resistance
25
50
75
KW
Ci(CANH)
Input capacitance at pin CANH
VTxD = VCC; not tested
7.5
20
pF
Ci(CANL)
Input capacitance at pin CANL
VTxD = VCC; not tested
7.5
20
pF
Ci(dif)
Differential input capacitance
VTxD = VCC; not tested
3.75
10
pF
ILI(CANH)
Input leakage current at pin CANH
VCC = 0 V; VCANH = 5V
10
170
250
mA
ILI(CANL)
Input leakage current at pin CANL
VCC = 0 V; VCANL = 5V
10
170
250
mA
VCMpeak
Commonmode peak during transition
from dom → rec or rec → dom
500
mV
VCMstep
Difference in commonmode between
dominant and recessive state
150
mV
POWERONRESET (POR)
PORL
POR level
CANH, CANL, Vref in tri
state below POR level
2.2
3.5
4.5
V
THERMAL SHUTDOWN
Tj(sd)
Shutdown junction temperature
150
160
180
°C
td(TxDBUSon)
Delay TxD to bus active
Vs = 0 V
40
85
130
ns
td(TxDBUSoff)
Delay TxD to bus inactive
Vs = 0 V
30
60
105
ns
td(BUSonRxD)
Delay bus active to RxD
Vs = 0 V
25
55
105
ns
td(BUSoffRxD)
Delay bus inactive to RxD
Vs = 0 V
65
100
135
ns
tpd(recdom)
Propagation delay TxD to RxD from
recessive to dominant
Vs = 0 V
70
245
ns
td(domrec)
Propagation delay TxD to RxD from
dominant to recessive
Vs = 0 V
100
245
ns
tdom(TxD)
TxD dominant time for time out
VTxD = 0 V
250
450
750
ms
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