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| 型號： | AMIS-722402 |
| 英文描述： | Contact Image Sensor |
| 中文描述： | 接觸式圖像傳感器 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 655K |
| 代理商： | AMIS-722402 |
AMIS-722402: Contact Image Sensor
Data Sheet
8.0 Timing Requirements
Table 6 lists the timing requirements for all four resolution modes, and their associated timing diagrams are shown in Figures 4-9.
Table 6: Timing Requirements
Parameter
Symbol
Min.
Typ.
Clock (CLK) period
CLKp
330
400
Clock (CLK) pulse width
CLKpw
200
Clock (CLK) duty cycle
50
Data setup time
Tset
20
Data hold time
(1)
Thold
25
Clock (CLK) rise time
(2)
CLKrt
70
Clock (CLK) fall time
(2)
CLKft
70
End-of-scan (SO) rise time
(2)
SOrt
End-of-scan (SO) fall time
(2)
SOft
Global start (GBST) rise time
(3)
GBSTrt
70
Global start (GBST) fall time
(3)
GBSTft
70
Pixel rise time
(4,5)
Prt
Pixel fall time
(4,5)
Pft
Notes:
1.
The shift register will load on all falling CLK edges, so setup and hold times (Tset, Thold) are needed to prevent the loading of multiple start pulses. This would
occur if the GBST remains high during two fallings edges of the CLK signal. See Figure 8.
2.
SI starts the register scanning and the first active pixel is read out on the 76
clock of the CLK signal. However, when multiple sensors are sequentially scanned,
as in CIS modules, the SO from the predecessor sensor becomes the SI to the subsequent sensor, hence the SI clock = the SO clock.
3.
As discussed under the third unique feature, the GBST starts the initialization process and preprocesses all sensors simultaneously in the first 75 clock cycles
before the first pixel is scanned onto the video line from the first sensor.
4.
The transition between pixels does not always reach the dark offset level as shown in the timing diagrams, see Vout. The timing diagrams show the transition
doing so for illustration purposes; however a stable pixel sampling point does exist for every pixel.
5.
The pixel rise time is defined as the time from when the CLK’s rising edge has reached 50 percent of its maximum amplitude to the point when a pixel has reached
90 percent of its maximum amplitude. The pixel fall time is defined as the time from when the CLK’s falling edge has reached 50 percent of its maximum amplitude
to the point when a pixel has reached 10 percent of its maximum amplitude.
Figures 4, 5, 6, and 7 show the initialization of the first sensor in relation to its subsequent cascaded sensors for all four resolution
modes. The SIC selects the first sensor to operate with 75 clock cycles of delay by connecting it to Vdd on the first sensor and to
Ground for all of the subsequent sensors. Hence the first sensor will operate with 75 inactive pixels being clocked out before its first
active pixel is clocked out.
GBST
Max.
2000
50
50
100
30
Units
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1376 Active Pixels (1376 Clocks)
VOUT
75 Inactive Pixels (75 Clocks)
SO
CLK
2
1
72
3
74
73
76
75
78
77
1442
79
1444
1443
1451
1448
1447
1450
1449
1
1374
1373
1372
2
3
4
1367
1368
1369
1376
1375
Figure 4: Overall Timing Diagram for the 2400dpi Mode
9
AMI Semiconductor
– Jan. 06, M-20499-004
www.amis.com
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