
AMIS-42665 High-Speed Low Power CAN Transceiver
Data Sheet
The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 4). Pins TxD and
STB are pulled high internally should the input become disconnected. Pins TxD, STB and RxD will be floating, preventing reverse
supply should the V
CC
supply be removed.
8.0 Electrical Characteristics
8.1 Definitions
All voltages are referenced to GND (pin 2). Positive currents flow into the IC. Sinking current means the current is flowing into the pin;
sourcing current means the current is flowing out of the pin.
8.2 Absolute Maximum Ratings
Stresses above those listed in the following table may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may effect device reliability.
Table 4: Absolute Maximum Ratings
Symbol
Parameter
V
CC
Supply voltage
V
CANH
DC voltage at pin CANH
V
CANL
DC voltage at pin CANL
V
SPLIT
DC voltage at pin VSPLIT
V
TxD
DC voltage at pin TxD
V
RxD
DC voltage at pin RxD
V
STB
DC voltage at pin STB
V
tran(CANH)
Transient voltage at pin CANH
V
tran(CANL)
Transient voltage at pin CANL
V
tran(VSPLIT)
Transient voltage at pin VSPLIT
V
esd(CANL/CANH/
Electrostatic discharge voltage at CANH and CANL pin
Conditions
0 < V
CC
< 5.25V; no time limit
0 < V
CC
< 5.25V; no time limit
0 < V
CC
< 5.25V; no time limit
Note 1
Note 1
Note 1
Note 2
Note 4
Note 2
Note 4
Note 3
Min.
-0.3
-50
-50
-50
-0.3
-0.3
-0.3
-300
-300
-300
-8
-500
-5
-500
-55
-40
-40
Max.
+7
+50
+50
+50
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
+300
+300
+300
+8
+500
+5
+500
120
+150
+125
+170
Unit
V
V
V
V
V
V
V
V
V
V
kV
V
kV
V
mA
°C
°C
°C
VSPLIT)
V
esd
Electrostatic discharge voltage at all other pins
Latch-up
T
stg
T
amb
T
junc
Static latch-up at all pins
Storage temperature
Ambient temperature
Maximum junction temperature
Notes:
1) Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b (see Figure 4).
2) Standardized human body model electrostatic discharge (ESD) pulses in accordance to MIL883 method 3015.7.
3) Static latch-up immunity: Static latch-up protection level when tested according to EIA/JESD78.
4) Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993.
8.3 Thermal Characteristics
Table 5: Thermal Characteristics
Symbol
Parameter
R
th(vj-a)
Thermal resistance from junction to ambient in SO8 package
R
th(vj-s)
Thermal resistance from junction to substrate of bare die
Conditions
In free air
In free air
Value
145
45
Unit
K/W
K/W
5
AMI Semiconductor
– Rev. 3.1, April 06
www.amis.com