參數(shù)資料
型號： AME8550AEETA300Y
廠商： AME, Inc.
英文描述： Voltage Detector
中文描述： 電壓檢測器
文件頁數(shù)： 13/21頁
文件大?。?/td> 280K
代理商： AME8550AEETA300Y
AME, Inc.
13
AME8550
Voltage Detector
1. When input voltage (V
DD
) rises above detect voltage
(V
DF
), output voltage (V
OUT
) will be equal to V
DD
.
( A condition of high impedance exists with Nch open
drain output configurations. )
2. When input voltage (V
DD
) falls below detect voltage
(V
), output voltage (V
OUT
) will be equal to the ground
voltage (V
SS
) level.
3. When input voltage (V
) falls to a level below that of
the minimum operating voltage (V
), output will become
unstable. In this condition, V
will equal the pulled-up
output ( should output be pulled-up.)
4. When input voltage (V
) rises above the ground volt-
age (V
) level, output will be unstable at levels below the
minimum operating voltage (V
). Between the V
and
detect release voltage (V
DR
) levels, theground voltage (V
SS
)
level will be maintained.
5. When input voltage (V
) rises above detect release
voltage (V
), output voltage (V
OUT
) will be equal to V
DD
after T
D
delay time.
Q = V x C
= I x T
D
VxC
T= V=V
REF
I
For Example, T
D
=
( A condition of high impedance exists with Nch open
drain output configurations. )
6. The difference between V
DR
and V
DF
represents the
hysteresis range.
n
Functional Description
(CMOS output without delay)
1. When input voltage (V
DD
) rises above detect voltage
(V
DF
), output voltage (V
OUT
) will be equal to V
DD
.
( A condition of high impedance exists with Nch open
drain output configurations. )
2. When input voltage (V
DD
) falls below detect voltage
(V
), output voltage (V
OUT
) will be equal to the ground
voltage (V
SS
) level.
3. When input voltage (V
) falls to a level below that of
the minimum operating voltage (V
), output will become
unstable. In this condition, V
will equal the pulled-up
output ( should output be pulled-up.)
4. When input voltage (V
) rises above the ground volt-
age (V
) level, output will be unstable at levels below the
minimum operating voltage (V
). Between the V
and
detect release voltage (V
DR
) levels, theground voltage (V
SS
)
level will be maintained.
5. When input voltage (V
) rises above detect release
voltage (V
DR
), output voltage (V
OUT
) will be equal to V
DD
.
( A condition of high impedance exists with Nch open
drain output configurations. )
6. The difference between V
DR
and V
DF
represents the
hysteresis range.
n
Timing Chart
n
Functional Description
(CMOS output with delay)
n
Timing Chart
Detect Voltage (V
DF
)
Min. Operating Voltage (V
MIN
)
Ground Voltage (V
ss
)
Output Voltage (V
OUT
)
Ground Voltage (V
ss
)
Detect Release Voltage (V
DR
)
Input Voltage (V
DD
)
1
2
3
4
5
6
T
D
Detect Voltage (V
DF
)
Min. Operating Voltage (V
MIN
)
Ground Voltage (V
ss
)
Output Voltage (V
OUT
)
Ground Voltage (V
ss
)
Detect Release Voltage (V
DR
)
Input Voltage (V
DD
)
1
2
3
4
5
6
V
REF
* 1nF
75nA
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