參數(shù)資料
型號: AMD1027
廠商: Analog Devices, Inc.
英文描述: dBCOOL Remote Thermal Controller and Voltage Monitor
中文描述: dBCOOL遠程熱控制器和電壓監(jiān)視器
文件頁數(shù): 19/56頁
文件大?。?/td> 1072K
代理商: AMD1027
REV. A
ADM1027
–19–
SMBALERT
INTERRUPT BEHAVIOR
The ADM1027 can be polled for status, or an
SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the
SMBALERT
output and status bits
behave when writing interrupt handler software.
STICKY
STATUS
BIT
HIGH LIMIT
TEMPERATURE
SMBALERT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
Figure 16.
SMBALERT
and Status Bit Behavior
Figure 16 shows how the
SMBALERT
output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. The status bits are referred
to as sticky since they remain set until read by software. This
ensures that an out-of-limit event cannot be missed if software
is polling the device periodically. Note that the
SMBALERT
output remains low for the entire duration that a reading is
out-of-limit and until the status register has been read. This has
implications on how software handles the interrupt.
HANDLING
SMBALERT
INTERRUPTS
To prevent the system from being tied up servicing interrupts,
it is recommend to handle the
SMBALERT
interrupt as follows:
1. Detect the
SMBALERT
assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt source.
4. Mask the interrupt source by setting the appropriate mask bit
in the interrupt mask registers (Reg. 0x74, 0x75).
5. Take the appropriate action for a given interrupt source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the interrupt status bit
has cleared, reset the corresponding interrupt mask bit to 0.
This will cause the
SMBALERT
output and status bits to
behave as shown in Figure 17.
STICKY
STATUS
BIT
HIGH LIMIT
TEMPERATURE
SMBALERT
CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
INTERRUPT MASK
BIT CLEARED
(
SMBALERT
REARMED)
Figure 17. How Masking the Interrupt Source
Affects
SMBALERT
Output
MASKING INTERRUPT SOURCES
Interrupt Mask Registers 1 and 2 are located at Addresses 0x74
and 0x75. These allow individual interrupt sources to be masked
out to prevent
SMBALERT
interrupts. Note that masking an
interrupt source prevents only the
SMBALERT
output from
being asserted; the appropriate status bit will be set as normal.
INTERRUPT MASK REGISTER 1 (REG. 0x74)
Bit 7 (OOL) = 1,
set this bit to 1 to allow masking of interrupts
by Status Register 2. If this bit = 0, then setting a bit in Mask
Register 2 to 1 will have no effect.
Bit 6 (R2T) = 1,
masks
SMBALERT
for Remote 2 temperature.
Bit 5 (LT) = 1,
masks
SMBALERT
for local temperature.
Bit 4 (R1T) = 1,
masks
SMBALERT
for Remote 1 temperature.
Bit 3 (5 V) = 1,
masks
SMBALERT
for 5 V channel.
Bit 2 (V
CC
) = 1,
masks
SMBALERT
for V
CC
channel.
Bit 1 (V
CCP
) = 1,
masks
SMBALERT
for V
CCP
channel.
Bit 0 (2.5 V) = 1,
masks
SMBALERT
for 2.5 V channel.
INTERRUPT MASK REGISTER 2 (REG. 0x75)
Bit 7 (D2) = 1,
masks
SMBALERT
for Diode 2 errors.
Bit 6 (D1) = 1,
masks
SMBALERT
for Diode 1 errors.
Bit 5 (FAN4) = 1,
masks
SMBALERT
for Fan 4.
Bit 4 (FAN3) = 1,
masks
SMBALERT
for Fan 3.
Bit 3 (FAN2) = 1,
masks
SMBALERT
for Fan 2.
Bit 2 (FAN1) = 1,
masks
SMBALERT
for Fan 1.
Bit 1 (OVT) = 1,
masks
SMBALERT
for overtemperature
(exceeding THERM limits).
Bit 0 (12 V) = 1,
masks
SMBALERT
for 12 V channel.
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