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參數(shù)資料
| 型號(hào)： | AMC020DFLKA |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | Circular Connector; No. of Contacts:37; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| 中文描述： | 20M X 8 FLASH 5V PROM CARD, 150 ns, XMA68 |
| 文件頁數(shù)： | 11/46頁 |
| 文件大?。?/td> | 157K |
| 代理商： | AMC020DFLKA |
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AmC0XXDFLKA
11
Table 4.
Odd Byte Command Definitions (Notes 1–5)
* Address for Memory Segment 1 (S1) only. Address for the higher odd memory segments (S3–S15) = (Addr) + ((N–1)/2)*
400000H + 20000H where N = Memory Segment number (1) for 4 Mbyte, N = (1, 3) for 8 Mbyte, N = (1, 3, 5) for 12 Mbyte,
N = (1…9) for 20 Mbyte, N = (1...15) for 32 Mbyte.
Notes:
1. Address bits = X = Don’t Care for all address commands except for Program Address (PA), Read Address (RA) and Sector
Address (SA).
2. Bus operations are defined in Table 1.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WEpulse.
SA = Address of the sector to be erased. The combination of A17, A18, A19, A20, A21 will uniquely select any sector of a
segment.
To select the memory segment:
4 Mbyte:
Use CE2
8 Mbyte:
Use CE2 and A22
20 and 32 Mbyte:
Use CE2 and A22–A24.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WEpulse.
5. A0 = 1 and CE1 = 0 or A0 = X and CE2 = 0.
Embedded
Command
Sequence
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Addr*
Data
Addr*
Data
Addr*
Data
Addr*
Data
Addr*
Data
Addr*
Data
Reset/Read
1
XXXXH
F0
Reset/Read
4
XXXXH
AA
XXXXH
55
XXXXH
F0
RA
RD
Autoselect
4
XXXXH
AA
XXXXH
55
XXXXH
90
00H
01
02H
3D
Byte Write
4
XXXXH
AA
XXXXH
55
XXXXH
A0
PA
PD
Segment Erase
6
XXXXH
AA
XXXXH
55
XXXXH
80
XXXXH
AA
XXXXH
55
XXXXH
10
Sector Erase
6
XXXXH
AA
XXXXH
55
XXXXH
80
XXXXH
AA
XXXXH
55
SA
30
Sector Erase Suspend
XXXXH
AA
Erase can be suspended during sector erase with Addr (don’t care), Data (B0H)
Sector Erase Resume
XXXXH
AA
Erase can be resumed after suspend with Addr (don’t care), Data (30H)
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PDF描述 |
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| AMD-645 | Peripheral Bus Controller(外圍總線控制器) |
| AMD-751 | System Bus, System Memory Controller, AGP Controller, and PCI Bus Controller(系統(tǒng)總線、系統(tǒng)存儲(chǔ)器控制器、AGP控制器和PCI總線控制器) |
| AMD-756 | Peripheral Bus Controller(外圍總線控制器) |
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