- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366552 > AM85C30-8BUA (Advanced Micro Devices, Inc.) Enhanced Serial Communications Controller PDF資料下載
參數(shù)資料
| 型號： | AM85C30-8BUA |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced Serial Communications Controller |
| 中文描述： | 增強的串行通信控制器 |
| 文件頁數(shù)： | 31/68頁 |
| 文件大小： | 553K |
| 代理商： | AM85C30-8BUA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
AMD
31
Am85C30
Auto RTS Reset
On the CMOS ESCC, if bit D
0
of WR15 and bit D
2
of
WR7
′
are set to 1 and the channel is in SDLC mode, the
RTS
pin may be reset early in the Tx Underrun routine
and the
RTS
pin will remain active until the last 0 bit of
the closing flag leaves the TxD pin as shown in Figure
16. Note that in order for this to function properly, bits D
3
and D
2
of WR10 must be set to 1 and 0, respectively.
CRC Character Reception
NMOS Am8530H
On the NMOS Am8530H, when the end-of-frame flag is
detected, the contents of the Receive Shift Register are
transferred to the Receive Data FIFO regardless of the
number of bits accumulated. Because of the 3-bit delay
between the Receive SYNC Register and Receive Shift
Register, the last 2 bits of the CRC check character
received are never transferred to the Receive Data
FIFO. Thus, the received CRC characters are unavail-
able for use.
CMOS Am85C30
On the Am85C30, the option of being able to receive the
complete CRC characters generated by the transmitter
is provided when both bit D
0
of WR15 and bit D
5
of WR7
′
are set to 1. When these 2 bits are set and an end-of-
frame flag is detected, the last 2 bits of the CRC will
be clocked into the Receive Shift Register before its
contents are transferred to the Receive Data FIFO. The
data-CRC boundary and CRC character bit formats for
each Residue Code provided are shown in Figures 17A
through 17D for each character length selected.
Data Being Sent
Data
CRC
CRC
Flag
Tx Underrun/EOM
RTS Bit D
1
WR5
RTS Pin (Active Low)
Figure 16. Auto
RTS
Reset Mode
10216F-20
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-16 | Enhanced Serial Communications Controller |
| AM85C30-8 | Enhanced Serial Communications Controller |
| AM85C30-8BQA | Enhanced Serial Communications Controller |
| AM8T-1203SC | 8 watt dc-dc converters |
| AM8T-1205DC | 8 watt dc-dc converters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM85C308JC | 制造商:AMD 功能描述:* |
| AM85C30-8JC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Enhanced Serial Communications Controller |
| AM85C308PC | 制造商:AMD 功能描述:_ |
| AM85C30-8PC | 制造商:AMD 功能描述:_ |
| AM85C80-16JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。