參數(shù)資料
型號: AM85C30-8BQA
廠商: Advanced Micro Devices, Inc.
英文描述: Enhanced Serial Communications Controller
中文描述: 增強的串行通信控制器
文件頁數(shù): 48/68頁
文件大?。?/td> 553K
代理商: AM85C30-8BQA
AMD
48
Am85C30
1
TdRXC(REQ)
RXC
W
/
REQ
Valid Delay
(Note 2)
RXC
to Wait Inactive Delay
(Notes 1, 2)
RxC
to
SYNC
Valid Delay
(Note 2)
RxC
to
INT
Valid Delay
(Notes 1, 2)
TxC
to
W
/
REQ
Valid Delay
(Note 3)
TxC
to Wait Inactive Delay
(Notes 1, 3)
TxC
to
DTR
/
REQ
Valid Delay
(Note 3)
TxC
to
DTR
/
REQ
Valid Delay
(Notes 3, 4)
TxC
to
INT
Valid Delay
(Notes 1, 3)
SYNC
Transition to
INT
Valid
Delay (Note 1)
DCD
or
CTS
Transition to
INT
Valid Delay (Note 1)
8
12
TcPc
2
TdRXC(W)
8
14
TcPc
3
TdRXC(SY)
4
7
TcPc
4
TdRXC(INT)
10
16
TcPc
5
TdTXC(REQ)
5
8
TcPc
6
TdTXC(W)
5
11
TcPc
7a
TdTXC(DRQ)
4
7
TcPc
7b
TdTXC(EDRQ)
5
8
TcPc
8
TdTXC(INT)
6
10
TcPc
9
TdSY(INT)
2
6
TcPc
10
TdEXT(INT)
2
6
TcPc
1
TdRXC(REQ)
RXC
W
/
REQ
Valid Delay
(Note 2)
RXC
to Wait Inactive Delay
(Notes 1, 2)
RxC
to
SYNC
Valid Delay
(Note 2)
RxC
to
INT
Valid Delay
(Notes 1, 2)
TxC
to
W
/
REQ
Valid Delay
(Note 3)
TxC
to Wait Inactive Delay
(Notes 1, 3)
TxC
to
DTR
/
REQ
Valid Delay
(Note 3)
TxC
to
DTR
/
REQ
Valid Delay
(Notes 3, 4)
TxC
to
INT
Valid Delay
(Notes 1, 3)
SYNC
Transition to
INT
Valid
Delay (Note 1)
DCD
or
CTS
Transition to
INT
Valid Delay (Note 1)
8
12
8
12
TcPc
2
TdRXC(W)
8
14
8
14
TcPc
3
TdRXC(SY)
4
7
4
7
TcPc
4
TdRXC(INT)
10
16
10
16
TcPc
5
TdTXC(REQ)
5
8
5
8
TcPc
6
TdTXC(W)
5
11
5
11
TcPc
7a
TdTXC(DRQ)
4
7
4
7
TcPc
7b
TdTXC(EDRQ)
5
8
5
8
TcPc
8
TdTXC(INT)
6
10
6
10
TcPc
9
TdSY(INT)
2
6
2
6
TcPc
10
TdEXT(INT)
2
6
2
6
TcPc
Notes
:
1. Open-drain output, measured with open-drain test load.
2.
RxC
is
RTxC
or
TRxC
, whichever is supplying the receive clock.
3.
TxC
is
TRxC
or
RTxC
, whichever is supplying the transmit clock.
4. Parameter applies to Enhanced Request mode only.
No.
Parameter
Symbol
Parameter
Description
8.192 MHz
10 MHz
Min
Max
Min
Max
Unit
No.
Parameter
Symbol
Parameter
Description
16.384 MHz
Min
Max
Unit
SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range
(continued)
System Timing (see Figure 20)
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