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參數(shù)資料
| 型號(hào)： | AM79C90PC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| 中文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 40/62頁 |
| 文件大?。?/td> | 437K |
| 代理商： | AM79C90PC |
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AMD
P R E L I M I N A R Y
40
Am79C90
SWITCHING CHARACTERISTICS (continued)
Parameter
No. Symbol Parameter Description
Test
Conditions
Min
Typ
Max
Unit
55
t
SAH
ADR Hold Time After the Rising Edge of
DAS
(Bus Slave)
0
ns
56
t
SAS
ADR Setup Time to the Falling Edge of
DAS
(Bus Slave)
0
ns
57
t
ARYD
Delay from the Falling Edge of ALE to the
Falling Edge of
READY
to insure a
Minimum Bus Cycle Time (600 ns)
80
ns
(Note 5)
58
t
SRDS
Data Setup Time to the Falling Edge of
READY
(Bus Slave Read)
75
ns
59
t
RDYH
READY
Hold Time After the Rising Edge of
DAS
(Bus Master)
0
ns
60
t
SR01
READY
Driver Turn On After the Falling
Edge of
DAS
(Bus Slave)
(CSR0, CSR3, RAP)
(Notes 4, 6)
6t
TCT
ns
61
t
SR02
READY
Driver Turn On After the Falling
Edge of
DAS
(Bus Slave)
(CSR1, 2)
(Note 6)
14t
TCT
ns
62
t
SRYH
READY
Hold Time After the Rising Edge
of
DAS
(Bus Slave)
0
35
ns
63
t
SRH
READ Hold Time After the Rising Edge of
DAS
(Bus Slave)
0
ns
64
t
SRS
READ Setup Time to the Falling Edge of
DAS
(Bus Slave)
0
ns
65
t
CHL
TCLK Rising Edge to
HOLD
LOW or High
Delay
95
ns
66
t
CAV
TCLK to Address Valid
100
ns
67
t
CCA
TCLK Rising Edge to Control Signals Active
75
ns
68
t
CALE
TCLK Falling Edge to ALE LOW
90
ns
69
t
CDL
TCLK Falling Edge to
DAS
Falling Edge
90
ns
70
t
RCS
Ready Setup Time to TCLK Falling Edge
(Note 5)
0
ns
71
t
CDH
TCLK Rising Edge to
DAS
HIGH
90
ns
72
t
HCS
HLDA
Setup to TCLK Falling Edge
0
ns
73
t
RENH
RENA Hold Time After the Rising Edge of
RCLK
0
ns
74
t
CSR
CS
recovery time between deassertion
of
CS
or
HOLD
and assertion of
CS
t
TCT
+60
ns
Notes:
1. Not shown in the timing diagrams, specifies the minimum bus cycle for a single DMA data transfer. Tested by functional data
pattern.
2. Applicable parameters associated with Receive circuit are tested at t
RCT
(RCLK Period) = 100 ns, t
TCT
= 100 ns
(TCLK Period).
3. Not tested.
4. CSR0 write access time (t
SR01
) when STOP bit is being set can be as long as 12t
TCT
.
5. It is guaranteed that no wait states will be added by the C-LANCE if either parameter #57 or #70 is met.
6. Parameter is for design reference only.
7. Reset must be asserted for at least two rising and two falling edges of TCLK for the device to be reset. If reset is deasserted
before TCLK starts, the device behavior is undefined.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C90PCTR | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| AM79C930 | PCnet-Mobile Single-Chip Wireless LAN Media Access Controller |
| AM79C930VCW | PCnet-Mobile Single-Chip Wireless LAN Media Access Controller |
| AM79C940VCW | Media Access Controller for Ethernet (MACE) |
| AM79C940 | Media Access Controller for Ethernet (MACE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C90PCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C90PCTR | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| AM79C90WW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C930 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-Mobile Single-Chip Wireless LAN Media Access Controller |
| AM79C930EVAL-HW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C930EVAL-HW - PCnet-Mobile Evaluation Kit |
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