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參數(shù)資料
| 型號： | AM79C90JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| 中文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 25/62頁 |
| 文件大?。?/td> | 437K |
| 代理商： | AM79C90JC |
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P R E L I M I N A R Y
AMD
25
Am79C90
Bit
Name
Description
In loopback mode, transmit data
chaining is not possible. Receive
data chaining is possible if receive
buffers are 32 bytes long to allow
time for lookahead.
DISABLE
THE
causes the C-LANCE to not access
the Transmitter Descriptor Ring, and
therefore, no transmissions are at-
tempted. DTX = 1 will clear the
TXON bit in CSR
0
when initialization
is complete.
DISABLE THE RECEIVER causes
the C-LANCE to reject all incoming
packets and not access the Receive
Descriptor Ring. DRX = 1 will clear
the RXON bit in the CSR
0
when in-
itialization is complete.
01
DTX
TRANSMITTER
00
DRX
‘0’
47
1 0
PADR (47:01)
17881B-20
47:00
PADR
PHYSICAL ADDRESS is the unique
48-bit physical address assigned to
the C-LANCE. PADR (0) must be
zero.
Logical Address Filter
63
0
17881B-21
LADRF
63:00
LADRF
The 64-bit mask used by the
C-LANCE
to
addresses.
accept
logical
The purpose of logical (or group or multicast) addresses
is to allow a group of nodes in a network to receive the
same message. Each node can maintain a list of multi-
cast addresses that it will respond to. The logical ad-
dress filter mechanism in the C-LANCE is a hardware
aide that reduces the average amount of host computer
time required to determine whether or not an incoming
packet with a multicast destination address should be
accepted.
The logical address filter hardware is an implementation
of a hash code searching technique commonly used by
software programmers. If the multicast bit of the desti-
nation address of an incoming packet is set, the
hardware maps this address into one of 64 categories
which correspond to 64 bits in the Logical Address Filter
Register. The hardware then accepts or rejects the
packet depending on the state of the bit in the Logical
Address Filter Register which corresponds to the se-
lected category. For example, if the address maps into
category 24, and bit 24 of the logical address filter regis-
ter is set, the packet is accepted.
A node can be made a member of several groups by set-
ting the appropriate bits in the logical address filter
register.
The details of the hardware mapping algorithm are as
follows:
If the first bit of an incoming address is a “1” [PADR (0)
=1], the address is deemed logical and is passed
through the logical address filter.
The logical address filter is a 64-bit mask composed of
four sixteen-bit registers, LADRF (63:00) in the initiali-
zation block, that is used to accept incoming Logical Ad-
dresses. The incoming address is sent through the CRC
circuit. After all 48 bits of the address have gone through
the CRC circuit, the high order 6 bits of the resultant
CRC (32-bit CRC) are strobed into a register. This regis-
ter is used to select one of the 64-bit positions in the
Logical Address Filter. If the selected filter bit is a “1,” the
address is accepted and the packet will be put in mem-
ory. The logical address filter only assures that there is a
possibility that the incoming logical address belongs to
the node. To determine if it belongs to the node, the in-
coming logical address that is stored in main memory is
compared by software to the list of logical addresses to
be accepted by this node.
The task of mapping a logical address to one of 64-bit
positions requires a simple computer program (see Ap-
pendix A) which uses the same CRC algorithm (used in
C-LANCE and defined per Ethernet) to calculate the
HASH (see Figure 7).
Driver software that manages a list of multicast ad-
dresses can work as follows. First the multicast address
list and the logical address filter must be initialized.
Some sort of management function such as the driver
initialization routine passes to the driver a list of ad-
dresses. For each address in the list the driver uses a
subroutine similar to the one listed in the appendix to set
the appropriate bit in a software copy of the logical ad-
dress filter register. When the complete list of addresses
has been processed, the register is loaded.
Later, when a packet is received, the driver first looks at
the Individual/Group bit of the destination address of the
packet to find out whether or not this is a multicast ad-
dress. If it is, the driver must search the multicast ad-
dress list to see if this address is in the list. If it is not in
the list, the packet is discarded.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C90JC-G | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C90JCTR | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| AM79C90PC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| AM79C90PCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C90PCTR | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:CMOS Local Area Network Controller for Ethernet (C-LANCE) |
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