參數(shù)資料
型號(hào)： AM79C875KI
廠商： ADVANCED MICRO DEVICES INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： NetPHY⑩ 4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP100
封裝： 14 X 20 MM, PLASTIC, QFP-100
文件頁(yè)數(shù)： 28/48頁(yè)
文件大?。?/td> 2480K
代理商： AM79C875KI
28
Am79C875
PHY Identifier 1 Register (Register 2)
Table 9.
Reg
Bit
Name
Description
Read/
Write
Default
2
15:0
OUI
Composed of the 3rd through 18th bits of the Organizationally
Unique Identifier (OUI), respectively.
RO
0022(H)
PHY Identifier 1 Register (Register 2)
PHY Identifier 2 Register (Register 3)
Table 10.
Reg
Bit
Name
Description
Read/
Write
Default
3
15:10
OUI
Assigned to the 19th through 24th bits of the OUI.
RO
010101
3
9:4
Model Number
Six bit manufacturer’s model number.
RO
010100
3
3:0
Revision Number
Four bit manufacturer’s revision number. 0001 stands for
Rev. A, etc.
RO
0001
PHY Identifier 2 Register (Register 3)
Auto-Negotiation Advertisement Register (Register 4)
Table 11.
Reg
Bit
Name
Description
Read/
Write
Default
4
15
Next Page
1 = Next Page enabled.
0 = Next Page disabled.
RW
0
4
14
Acknowledge
This bit will be set internally after receiving 3 consecutive and
consistent FLP bursts.
RO
0
4
13
Remote Fault
1 = Remote fault supported.
0 = No remote fault.
RW
0
4
12:11
Reserved
Write as 0, ignore when read.
RW
0
4
10
FDFC
Full Duplex Flow Control.
1 = Advertise that the DTE(MAC) has implemented both the
optional MAC control sublayer and the pause function as
specified in clause 31 and annex 31 B of 802.3u.
0 = No MAC-based full duplex flow control.
RW
0
4
9
100BASE-T4
The NetPHY 4LP device does not support 100BASE-T4
function, i.e., this bit ties to zero.
RO
0
4
8
100BASE-TX
Full Duplex
1 = 100BASE-TX with full duplex.
0 = No 100BASE-TX full duplex ability.
Default is set by Register 1.14.
RW
Set by
DPLX pin
4
7
100BASE-TX
Half Duplex
1 = 100BASE-TX with half duplex.
0 = No 100BASE-TX half duplex capability.
Default is set by Register 1.13.
RW
1
4
6
10BASE-T
Full Duplex
1 = 10 Mbps with full duplex.
0 = No 10Mbps full duplex capability.
Default is set by Register 1.12.
RW
Set by
DPLX pin
4
5
10BASE-T
Half Duplex
1 = 10 Mbps with half duplex.
0 = No 10 Mbps half duplex capability
Default is set by Register 1.11.
RW
1
4
4:0
Selector Field
[00001] = IEEE 802.3
RO
00001
Auto-Negotiation Advertisement Register (Register 4)
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