- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364672 > AM5X86 Am5x86 - Am5x86 3.3-Volt Microprocessor Family PDF資料下載
參數(shù)資料
| 型號： | AM5X86 |
| 英文描述： | Am5x86 - Am5x86 3.3-Volt Microprocessor Family |
| 中文描述： | Am5x86 - Am5x86 3.3伏微處理器家族 |
| 文件頁數(shù)： | 31/67頁 |
| 文件大?。?/td> | 1585K |
| 代理商： | AM5X86 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁
Am5
X
86 Microprocessor
31
AMD
PRELIMINARY
Step 10In the same clock cycle, the snooping cache
drives HITM back to 1.
Step 11The write of data A is finished if BRDY transi-
tions to 0 (BLAST = 0), because it is a single
word.
The software write sequence was first data A and then
data B. But on the external bus the data appear first as
data B and then data A. The order of writes is changed.
In most cases, it is unnecessary to strictly maintain the
ordering of writes. However, some cases (for example,
writing to hardware control registers) require writes to
be observed externally in the same order as pro-
grammed. There are two options to ensure serialization
of writes, both of which drive the cache to Write-through
mode:
1.
2.
Set the PWT bit in the page table entries.
Drive the WB/WT signal Low when accessing these
memory locations.
Option 1 is an operating-system-level solution not di-
rectly implemented by user-level code. Option 2, the
hardware solution, is implemented at the system level.
BLAST
Data
BRDY
EADS
ADS
HITM
Cached Data
AHOLD
CLK
Write Buffer
B original
1
A
2
6
5
B modified
4
3
B
B+4
B+8
B+12
8
A
Ignored
9
7
XXX
Note:
The circled numbers in this figure represent the steps in section 4.8.7.1.
Figure 14. Write Cycle Reordering Due to Buffering
10
11
Step 3 The next write of the processor hits the cache
and the line is non-shared. Therefore, data B is
written into the cache. The cache line transits
to the modified state.
Step 4 In the same clock cycle, a snoop request to the
same address where data B resides is started
because EADS = 0. The snoop hits a modified
line. EADS is ignored due to the hit of a modified
line, but is detected again as early as in step 10.
Step 5 Two clock cycles after EADS asserts, HITM be-
comes valid.
Step 6 Because the processor-initiated access cannot
be finished (AHOLD is still 1), the BIU gives
priority to a write-back access that does not re-
quire the use of the address bus. Therefore, in
the clock cycle, the cache starts the write-back
sequence indicated by ADS = 0 and W/R = 0.
Step 7 During the write-back sequence, AHOLD is
deasserted.
Step 8 The write-back access is finished when BLAST
and BRDY transition to 0.
Step 9 After the last write-back access, the BIU starts
writing data A from the write buffers. This is
indicated by ADS = 0 and W/R = 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM685 | CBGA, COM TEMP(DATA FLASH) |
| AM685DE | Analog Comparator |
| AM685DL | SOIC, IND TEMP, GREEN(DATA FLASH) |
| AM685DLB | TSSOP, COM TEMP(DATA FLASH) |
| AM685HE | TSSOP, IND TEMP, GREEN(DATA FLASH) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM5X86-P75 | 制造商:Advanced Micro Devices 功能描述:Microprocessor, 32 Bit, 168 Pin, Ceramic, PGA |
| AM6 | 功能描述:按鈕開關(guān) Push Button Oper, 30 mm,Non Ill. Mush., Mom., Blue RoHS:否 制造商:C&K Components 觸點形式:2 NC - 2 NO 開關(guān)功能:ON ? OFF 電流額定值:4 A 電壓額定值 AC:12 V to 250 V 電壓額定值 DC:12 V to 50 V 功率額定值: 安裝風(fēng)格:Through Hole 照明:Illuminated 照明顏色:None IP 等級:IP 40 端接類型:Solder 觸點電鍍:Silver 執(zhí)行器:Square 蓋顏色: 封裝: 可燃性等級:UL 94 V-0 |
| AM-6 | 制造商:Greenlee Textron Inc 功能描述:MULTIMETER ANALOG 制造商:Greenlee Textron Inc 功能描述:MULTIMETER,ANALOG |
| AM60 | 制造商:Thomas & Betts 功能描述:60A ANGLE ADAPTER |
| AM600 | 制造商:EXTECH 制造商全稱:Extech Instruments Corporation. 功能描述:600A AC Analog Clamp Meter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。