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參數(shù)資料
| 型號： | AM50DL128BH |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:128; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 16/68頁 |
| 文件大?。?/td> | 959K |
| 代理商： | AM50DL128BH |
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14
Am50DL128BH
October 7, 2003
A D V A N C E I N F O R M A T I O N
may be initiated for simultaneous operation with zero
latency. I
CC6
f and I
CC7
f in the table represent the cur-
rent specifications for read-while-program and
read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at V
CC
± 0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE#f and RESET# are held at V
IH
, but not
within V
CC
± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (t
CE
) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
f in the table represents the standby current spec-
ification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC5
f in the table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
f). If RESET# is
held at V
IL
but not within V
SS
±0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
READY
(not during Embedded
Algorithms). The system can read data t
RH
after the
RESET# pin returns to V
IH
.
Refer to the pSRAM AC Characteristics tables for RE-
SET# parameters and to Figure 16 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM50DL128BH56I | Circular Connector; No. of Contacts:56; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AM50DL128BH56IS | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH56IT | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH70I | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH70IS | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM50DL128BH_04 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories |
| AM50DL128BH56I | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH56IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories |
| AM50DL128BH56IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories |
| AM50DL128BH70I | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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