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參數(shù)資料
| 型號(hào)： | AM50DL128BH70I |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | SRAM |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁(yè)數(shù)： | 59/68頁(yè) |
| 文件大?。?/td> | 959K |
| 代理商： | AM50DL128BH70I |
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October 7, 2003
Am50DL128BH
57
A D V A N C E I N F O R M A T I O N
pSRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1ps, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1ps, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
Figure 31.
Pseudo SRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
56, 70
85
t
WC
t
WP
t
CW
t
BW
t
AW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
t
CH
t
CEH
t
WEH
Write Cycle Time
Min
70
85
ns
Write Pulse Time
Min
50
60
ns
Chip Enable to End of Write
Min
60
70
ns
Data Byte Control to End of Write
Min
60
70
ns
Address Valid to End of Write
Min
60
70
ns
Address Setup Time
Min
0
ns
Write Recovery Time
Min
0
ns
WE# Low to Write to Output High-Z
Max
20
ns
WE# High to Write to Output Active
Min
0
ns
Data Set-up Time
Min
30
Data Hold from Write Time
Min
0
ns
CE2 Hold Time
Min
300
μs
Chip Enable High Pulse Width
Min
10
ns
Write Enable High Pulse Width
Min
6
ns
t
WC
t
WP
t
WR
t
CW
t
BW
Valid Data In
t
AS
t
CH
t
OEW
Addresses
A20 to A0
WE#
CE#1s
CE2s
LB#, UB#
D
IN
DQ15 to DQ0
D
OUT
DQ15 to DQO
t
ODW
t
DS
t
DH
High-Z
(Note 1)
(Note 3)
(Note 4)
相關(guān)PDF資料 |
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| AM50DL128BH70IS | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH70IT | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH85I | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH85IS | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM50DL128BH70IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories |
| AM50DL128BH70IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH85I | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH85IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories |
| AM50DL128BH85IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories |
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