參數(shù)資料
型號(hào): AM50DL128BH56IT
廠商: Advanced Micro Devices, Inc.
元件分類: SRAM
英文描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
中文描述: 堆疊式多芯片封裝(MCP)閃存和SRAM
文件頁數(shù): 41/68頁
文件大小: 959K
代理商: AM50DL128BH56IT
October 7, 2003
Am50DL128BH
39
A D V A N C E I N F O R M A T I O N
pSRAM DC & OPERATING CHARACTERISTICS
Notes:
1. V
CC
– 1.0 V for a 10 ns pulse width.
2. V
CC
+ 1.0 V for a 10 ns pulse width.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Leakage Current
V
IN
= V
SS
to V
CC
–1.0
1.0
μA
I
LO
Output Leakage Current
CE1#s = V
IH
, CE2s = V
IL
or OE# = V
IH
or
WE# = V
IL
, V
IO
= V
SS
to V
CC
–1.0
1.0
μA
I
CC1
s
Operating Current
Cycle time = Min., I
IO
= 0 mA, 100% duty,
CE1#s = V
IL
, CE2s = V
IH
, V
IN
= V
IL
= or V
IH
,
t
RC
= Min.
40
mA
I
CC2
s
Page Access Operating
Current
Cycle time = Min., I
IO
= 0 mA, 100% duty,
CE1#s = V
IL
, CE2s = V
IH
, V
IN
= V
IL
= or V
IH
,
t
PC
= Min.
25
mA
V
OL
Output Low Voltage
I
OL
= 1.0 mA
0.4
V
V
OH
Output High Voltage
I
OH
= –0.5 mA
2
V
I
SB
Standby Current (CMOS)
CE#1 = V
CCS
– 0.2 V, CE2 = V
CCS
– 0.2 V
70
μA
I
DSB
Deep Power-down Standby
CE2 = 0.2 V
5
μA
V
IL
Input Low Voltage
–0.3
(Note 1)
0.4
V
V
IH
Input High Voltage
2.4
V
CC
+
0.3
(Note 2)
V
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