
4
Am49PDL640AG
November 20, 2003
P R E L I M I N A R Y
Figure 20. Back-to-back Read/Write Cycle Timings ....................... 51
Figure 21. Data# Polling Timings (During Embedded Algorithms).. 51
Figure 22. Toggle Bit Timings (During Embedded Algorithms)....... 52
Figure 23. DQ2 vs. DQ6.................................................................. 52
Temporary Sector Unprotect ..................................................53
Figure 24. Temporary Sector Unprotect Timing Diagram............... 53
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram.............................................................. 54
Alternate CE#f Controlled Erase and Program Operations ....55
Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings........................................................................... 56
Power Up Time .......................................................................57
Figure 27. Power Up....................................................................... 57
Figure 28. VCCS Slew Rate............................................................ 57
Read Cycle .............................................................................58
Read Cycle .............................................................................59
Figure 29. pSRAM Read Cycle–Address Controlled ...................... 59
Figure 30. pSRAM Read Cycle–CS1# Controlled........................... 59
Write Cycle .............................................................................60
Figure 31. pSRAM Write Cycle–WE# Controlled........................... 61
Figure 32. pSRAM Write Cycle–CS1# Controlled.......................... 61
Figure 33. pSRAM Write Cycle–UB#, LB# Controlled ................... 62
Figure 34. Deep Power Down Mode.............................................. 62
Figure 35. Abnormal Timing........................................................... 63
Figure 36. Avoidable Timing 1 ....................................................... 63
Figure 37. Avoidable Timing 2 ....................................................... 63
Erase And Programming Performance . . . . . . . 64
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 64
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 64
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 64
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 65
FLK073—73-Ball Fine-Pitch Grid Array 13 x 9 mm ................65
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 66