參數(shù)資料
型號： AM49PDL640AG85NT
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 13 X 9 MM, FBGA-73
文件頁數(shù)： 47/69頁
文件大小： 491K
代理商： AM49PDL640AG85NT
November 20, 2003
Am49PDL640AG
45
P R E L I M I N A R Y
AC CHARACTERISTICS
Flash Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 18 for test specifications
3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V
CC
/2. The time from OE# high to
the data bus driven to V
CC
/2 is taken as t
DF
.
.
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
70
85
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
70
85
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
70
85
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
70
85
ns
t
PACC
Page Access Time
Max
25
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
25
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Notes 1, 3)
Max
25
30
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 3)
Max
25
30
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
4
5
ns
t
OEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
OH
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Figure 14.
Read Operation Timings
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