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| 型號(hào)： | AM49DL640AG |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | SRAM |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁數(shù)： | 56/65頁 |
| 文件大?。?/td> | 1005K |
| 代理商： | AM49DL640AG |
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April 1, 2003
Am49DL640AG
55
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 31.
pSRAM Write Cycle—WE# Control
Parameter
Symbol
Description
Speed
Unit
70
55
t
WC
Write Cycle Time
Min
70
55
ns
t
Cw
Chip Enable to End of Write
Min
60
50
ns
t
AS
Address Setup Time
Min
0
ns
t
AW
Address Valid to End of Write
Min
60
50
ns
t
BW
UB#s, LB#s to End of Write
Min
60
50
ns
t
WP
Write Pulse Time
Min
50
40
ns
t
WR
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Min
0
ns
Max
20
15
t
DW
Data to Write Time Overlap
Min
40
30
ns
t
DH
Data Hold from Write Time
Min
0
ns
t
OW
End Write to Output Low-Z
min
5
ns
Address
CE1#s
Data Undefined
WE#
Data In
Data Out
t
WC
t
CW
(See Note 1)
t
AW
High-Z
High-Z
Data Valid
CE2s
t
CW
(See Note 1)
t
WP
(See Note 4)
t
AS
(See Note 3)
t
WR
t
DW
t
DH
t
OW
t
WHZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM50DL128BH85IT | CA-BAYONET |
| AM50DL128BH | Circular Connector; No. of Contacts:128; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AM50DL128BH56I | Circular Connector; No. of Contacts:56; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AM50DL128BH56IS | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH56IT | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM49DL640AG70IS | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM49DL640AG70IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM49DL640AG85IS | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM49DL640AG85IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM49DL640AH | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM |
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