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參數(shù)資料
| 型號(hào)： | AM49DL640AG85IT |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封裝： | 8 X 11.60 MM, FBGA-73 |
| 文件頁數(shù)： | 59/65頁 |
| 文件大?。?/td> | 1005K |
| 代理商： | AM49DL640AG85IT |
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58
Am49DL640AG
April 1, 2003
P R E L I M I N A R Y
FLASH ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°
C, 3.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90
°
C, V
CC
= 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
12 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note:
Includes all pins except V
CC
. Test conditions: V
CC
= 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.4
5
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
56
sec
Byte Program Time
5
150
μs
Excludes system level
overhead (Note 5)
Accelerated Byte/Word Program Time
4
120
μs
Word Program Time
7
210
μs
Chip Program Time
(Note 3)
Byte Mode
42
126
sec
Word Mode
28
84
Description
Min
Max
Input voltage with respect to V
SS
on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/O pins
–1.0 V
V
CC
+ 1.0 V
V
CC
Current
–100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
11
14
pF
C
OUT
Output Capacitance
V
OUT
= 0
12
16
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
14
16
pF
C
IN3
WP#/ACC Pin Capacitance
V
IN
= 0
17
20
pF
Parameter Description
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
°
C
10
Years
125
°
C
20
Years
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM49DL640AG | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM50DL128BH85IT | CA-BAYONET |
| AM50DL128BH | Circular Connector; No. of Contacts:128; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AM50DL128BH56I | Circular Connector; No. of Contacts:56; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AM50DL128BH56IS | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AM49DL640AH | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM |
| AM49DL640AH56IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM |
| AM49DL640AH56IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM |
| AM49DL640AH70IS | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM |
| AM49DL640AH70IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) Pseudo Static RAM |
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