參數(shù)資料
型號(hào)： AM49DL32XBGT70IT
廠(chǎng)商： Spansion Inc.
英文描述： Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
中文描述： 堆疊式多芯片封裝（MCP）閃存和SRAM的32兆位（4個(gè)M × 8位/ 2米x 16位），3.0伏的CMOS只，同時(shí)
文件頁(yè)數(shù)： 57/64頁(yè)
文件大小： 570K
代理商： AM49DL32XBGT70IT
56
Am49DL32xBG
July 19, 2002
P R E L I M I N A R Y
pSRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. If the device is using the I/Os to output data, input signals of reverse polarity must not be applied.
2. If OE# is high during the write cycle, the outputs will remain at high impedance.
3. If CE#1s, LB# or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance.
4. If CE#1s, LB# or UB# goes high at the same time or before WE# goes high, the outputs will remain at high impedance.
Figure 30.
Pseudo SRAM Write Cycle
—
WE# Control
Parameter
Symbol
Description
Speed
Unit
70
85
t
WC
t
WP
t
CW
t
BW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
t
CH
Write Cycle Time
Min
70
85
ns
Write Pulse Time
Min
50
60
ns
Chip Enable to End of Write
Min
60
70
ns
Data Byte Control to End of Write
Min
60
70
ns
Address Setup Time
Min
0
ns
Write Recovery Time
Min
0
ns
WE# Low to Write to Output High-Z
Max
20
ns
WE# High to Write to Output Active
Min
0
ns
Data Set-up Time
Min
30
Data Hold from Write Time
Min
0
ns
CE2 Hold Time
Min
300
μs
t
WC
t
WP
t
WR
t
CW
t
BW
Valid Data In
t
AS
t
CH
t
OEW
Addresses
A0 to A20
WE#
CE#1
CE2
LB#, UB#
D
IN
I/O1 to 16
D
OUT
I/O1 to 16
t
ODW
t
DS
t
DH
High-Z
(Note 1)
(Note 3)
(Note 4)
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