參數(shù)資料
型號(hào): AM49BDS640AH
廠商: Spansion Inc.
英文描述: Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
中文描述: 堆疊多芯片封裝(MCP),閃存和1.8伏,只有同時(shí)讀/寫移動(dòng)存儲(chǔ)芯片的CMOS
文件頁數(shù): 75/84頁
文件大?。?/td> 763K
代理商: AM49BDS640AH
December 5, 2003
Am49BDS640AH
73
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Wait State Decoding Addresses:
A14, A13, A12 = “111”
Reserved
A14, A13, A12 = “110”
Reserved
A14, A13, A12 = “101”
5 programmed, 7 total
A14, A13, A12 = “100”
4 programmed, 6 total
A14, A13, A12 = “011”
3 programmed, 5 total
A14, A13, A12 = “010”
2 programmed, 4 total
A14, A13, A12 = “001”
1 programmed, 3 total
A14, A13, A12 = “000”
0 programmed, 2 total
Note:
Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.
Figure 45.
Example of Wait States Insertion
Data
AVD#
OE#
CLK
1
2
3
4
5
D0
D1
0
1
6
2
7
3
total number of clock cycles
following AVD# falling edge
Rising edge of next clock cycle
following last wait state triggers
next burst data
number of clock cycles
programmed
4
5
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