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參數資料
| 型號： | AM42DL1634DT70IT |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA69 |
| 封裝： | 8 X 11 MM, FBGA-69 |
| 文件頁數： | 55/61頁 |
| 文件大?。?/td> | 476K |
| 代理商： | AM42DL1634DT70IT |
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54
Am42DL16x4D
January 9, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
SRAM Write Cycle
Notes:
1. WE# controlled.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
6. If CE1# goes low (or CE2 goes high) at the same time or after WE# goes low, the outputs will remain at high impedance.
7. If CE1# goes high (or CE2 goes low) at the same time or before WE# goes high, the outputs will remain at high impedance.
8. If OE# is high during the write cycle, the outputs will remain at high impedance.
9. Output data may be present on the bus at this time; input signals should not be applied.
Figure 30.
SRAM Write Cycle
—
WE# Control
Parameter
Symbol
Description
Speed Options
Unit
70
85
t
WC
t
Cw
t
AS
t
AW
t
BW
t
WP
t
WR
Write Cycle Time
Min
70
85
ns
Chip Enable to End of Write
Min
60
70
ns
Address Setup Time
Min
0
ns
Address Valid to End of Write
Min
60
70
ns
UB#s, LB#s to End of Write
Min
60
70
ns
Write Pulse Time
Min
50
60
ns
Write Recovery Time
Min
0
ns
t
WHZ
Write to Output High-Z
Min
0
ns
Max
20
25
t
DW
t
DH
t
OW
Data to Write Time Overlap
Min
30
35
ns
Data Hold from Write Time
Min
0
ns
End Write to Output Low-Z
Min
5
ns
Address
CS1#s
UB#s, LB#s
WE#
Data In
Data Out
t
WC
t
CW
(See Note 2)
t
AW
High-Z
High-Z
Data Valid
CS2s
t
CW
(See Note 2)
t
BW
t
(See Note 5)
t
AS
(See Note 4)
t
WR
(See Note 3)
t
BW
t
DW
t
DH
t
OW
(See Note 9)
(See Note 9)
(See Note 7)
(See Note 6)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AM42DL1634DT85IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM |
| AM42DL1642DB30IS | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM |
| AM42DL1642DB30IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM |
| AM42DL1642DB35IS | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM |
| AM42DL1642DB35IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM |
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