參數(shù)資料
型號(hào): AM42BDS640AGTD9IS
廠商: SPANSION LLC
元件分類: 存儲(chǔ)器
英文描述: LJT 13C 13#22D SKT WALL RECP
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA93
封裝: 8 X 11.60 MM, FBGA-93
文件頁(yè)數(shù): 64/72頁(yè)
文件大?。?/td> 1060K
代理商: AM42BDS640AGTD9IS
November 1, 2002
Am42BDS640AG
63
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
Read Cycle
Note:
CE1#s = OE# = V
IL
, CE2s = WE# = V
IH
, UB#s and/or LB#s = V
IL
Figure 34.
SRAM Read Cycle—Address Controlled
Parameter
Symbol
Description
D8, D9
(54 MHz)
C8, C9
(40 MHz)
Unit
t
RC
Read Cycle Time
Min
70
85
ns
t
AA
Address Access Time
Max
70
85
ns
t
CO1
, t
CO2
Chip Enable to Output
Max
70
85
ns
t
OE
Output Enable Access Time
Max
35
40
ns
t
BA
LB#s, UB#s to Access Time
Max
70
85
ns
t
LZ1
, t
LZ2
Chip Enable (CE1#s Low and CE2s High) to Low-Z Output
Min
10
ns
t
BLZ
UB#, LB# Enable to Low-Z Output
Min
10
ns
t
OLZ
Output Enable to Low-Z Output
Min
5
ns
t
HZ1
, t
HZ2
Chip Disable to High-Z Output
Max
25
ns
t
BHZ
UB#s, LB#s Disable to High-Z Output
Max
25
ns
t
OHZ
Output Disable to High-Z Output
Max
25
ns
t
OH
Output Data Hold from Address Change
Min
10
ns
Address
Data Out
Previous Data Valid
Data Valid
t
AA
t
RC
t
OH
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