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參數(shù)資料
| 型號： | AM41PDS3228DT11IS |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 存儲器 |
| 英文描述： | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封裝： | 8 X 11.60 MM, FBGA-73 |
| 文件頁數(shù)： | 39/59頁 |
| 文件大小： | 560K |
| 代理商： | AM41PDS3228DT11IS |
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38
Am41PDS3228D
May 13, 2002
P R E L I M I N A R Y
FLASH AC CHARACTERISTICS
Read-Only Operations
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 12 for test specifications.
3. Measurements performed by placing a 50
termination on the data pin with a bias of V
CC
/2. The time from OE# high to the
data bus driven to V
CC
/2 is taken as t
DF
AC Characteristics.
Parameter
Description
Test Setup
Speed Option
JEDEC
Std
10
11
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
100
110
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
100
110
ns
t
PRC
Page Read Cycle
Min
40
45
ns
t
PACC
Page Address to Output Delay
CE#, OE# = V
IL
Max
40
45
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
100
110
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
35
45
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 3)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold
Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
OH
t
CE
Outputs
WE#
Addresses
CE#f
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
ACC
t
RC
t
OEH
t
RH
t
OE
t
RH
0 V
RY/BY#
RESET#
t
DF
Figure 15.
Conventional Read Operation Timings
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