參數(shù)資料
型號(hào): AM29SL800CB-100ED
廠商: SPANSION LLC
元件分類: PROM
英文描述: 512K X 16 FLASH 1.8V PROM, 100 ns, PDSO48
封裝: MO-142DD, TSOP-48
文件頁(yè)數(shù): 1/43頁(yè)
文件大小: 960K
代理商: AM29SL800CB-100ED
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 22230
Rev: D Amendment/+2
Issue Date: November 14, 2000
Refer to AMD’s Website (www.amd.com) for the latest information.
Am29SL800C
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 1.8 Volt-only Super Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
s Single power supply operation
— 1.8 to 2.2 V for read, program, and erase
operations
— Ideal for battery-powered applications
s Manufactured on 0.32 m process technology
— Compatible with 0.35 m Am29SL800B device
s High performance
— Access times as fast as 100 ns
s Ultra low power consumption (typical values at 5
MHz)
— 1 A Automatic Sleep Mode current
— 1 A standby mode current
— 5 mA read current
— 20 mA program/erase current
s Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
s Top or bottom boot block configurations
available
s Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
s Minimum 1,000,000 write cycle guarantee per
sector
s 20-year data retention at 125
°C
s Package option
— 48-pin TSOP
— 48-ball FBGA
s Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
s Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
s Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
s Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
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