
4
Am29PDL129H
August 8, 2003
P R E L I M I N A R Y
Figure 15. Program Operation Timings........................................... 53
Figure 16. Accelerated Program Timing Diagram........................... 53
Figure 17. Chip/Sector Erase Operation Timings........................... 54
Figure 18. Back-to-back Read/Write Cycle Timings....................... 55
Figure 19. Data# Polling Timings (During Embedded Algorithms).. 55
Figure 20. Toggle Bit Timings (During Embedded Algorithms)....... 56
Figure 21. DQ2 vs. DQ6.................................................................. 56
Temporary Sector Unprotect ..................................................57
Figure 22. Temporary Sector Unprotect Timing Diagram............... 57
Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram
58
Alternate CE# Controlled Erase and Program Operations .....59
Figure 24. Alternate CE# Controlled Write (Erase/Program)
OperationTimings.......................................................................... 60
Erase And Programming Performance. . . . . . . . 61
Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 61
BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 61
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
VBB080—80-Ball Fine-pitch Ball Grid Array
11.5x9mmpackage .............................................................62
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63