參數(shù)資料
型號(hào): AM29PL131DC
英文描述: User Programmable Special Function ASIC
中文描述: 用戶可編程ASIC的特殊功能
文件頁數(shù): 51/67頁
文件大?。?/td> 635K
代理商: AM29PL131DC
August 8, 2003
Am29PDL129H
49
P R E L I M I N A R Y
AC CHARACTERISTICS
CE1#/CE2# Timing
Read-Only Operations
Notes:
1.
2.
3.
Not 100% tested.
See
Figure 9
and
Table 17
for test specifications
Valid CE1#/CE2# conditions: (CE1#= V
IL
, CE2#= V
IH
) or (CE1#=
V
IH
, CE2#=V
IL
).
Valid CE1#/CE2# transitions: (CE1#= CE2#= V
IH
) to (CE1#= V
IL
,
CE2#=V
IH
) or (CE1#= V
IH
, CE2#=V
IL
).
4.
5.
Measurements performed by placing a 50 ohm termination on the
data pin with a bias of V
/2. The time from OE# high to the data
bus driven to V
CC
/2 is taken as t
DF
.
Valid CE1#/CE2# transitions: (CE1#= V
IL
, CE2#= V
IH
) or (CE1#=
V
IH
, CE2#=V
IL
) to (CE1#= CE2#= V
IH
).
6.
Parameter
Description
All Speed Options
Unit
JEDEC
Std
t
CCR
CE1#/CE2# Recover Time
Min
30
ns
CE1#
t
CCR
t
CCR
CE2#
Figure 11.
Timing Diagram for Alternating Between CE1# and CE2# Control
Parameter
Description
Test Setup
Speed Options
JEDEC
Std.
53
63
68
83, 88
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
55
65
85
ns
t
AVQV
t
ACC
Address to Output Delay (Note 3)
CE#, OE# = V
IL
Max
55
65
85
ns
t
ELQV
t
CE
Chip Enable to Output Delay (Note 4)
OE# = V
IL
Max
55
65
85
ns
t
PACC
Page Access Time
Max
20
25
30
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
20
25
30
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Notes 1, 5, 6)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Notes 1, 5)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE#/CE2#
or OE#, Whichever Occurs First (Notes 5, 6)
Min
5
ns
t
OEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
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