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參數(shù)資料
| 型號(hào)： | AM29PDL128G |
| 廠商： | Spansion Inc. |
| 英文描述： | High Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker 14-CDIP -55 to 125 |
| 中文描述： | 128兆位（8米× 16位/ 4米× 32位），3.0伏的CMOS只，同步讀/寫(xiě)閃存與VersatileIO控制記憶 |
| 文件頁(yè)數(shù)： | 33/69頁(yè) |
| 文件大?。?/td> | 1181K |
| 代理商： | AM29PDL128G |
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32
Am29PDL128G
July 29, 2002
P R E L I M I N A R Y
Table 12.
Device Geometry Definition
Addresses
(Double Word
Mode)
Addresses
(Word Mode)
Data
Description
27h
4Eh
0018h
Device Size = 2
N
byte
28h
29h
50h
52h
0005h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
2Ch
58h
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
00FDh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
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