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| 型號(hào)： | AM29PDL127H88PCI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | 8M X 16 FLASH 3V PROM, 85 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-64 |
| 文件頁(yè)數(shù)： | 53/68頁(yè) |
| 文件大?。?/td> | 750K |
| 代理商： | AM29PDL127H88PCI |
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June 30, 2003
Am29PDL127H
55
ADV ANCE
I N FO RMAT I O N
AC CHARACTERISTICS
OE#
CE#
WE#
Addresses
tOH
Data
Valid
In
Valid
In
Valid PA
Valid RA
tWC
tWPH
tAH
tWP
tDS
tDH
tAS
tRC
tCE
tAH
Valid
Out
tOE
tACC
tOEH
tGHWL
tDF
Valid
In
CE# Controlled Write Cycles
WE# Controlled Write Cycle
Valid PA
tCP
tCPH
tWC
Read Cycle
tSR/W
tAS
Figure 18.
Back-to-back Read/Write Cycle Timings
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ6–DQ0
RY/BY#
tBUSY
Complement
True
Addresses
VA
tOEH
tCE
tCH
tOH
tDF
VA
Status Data
Complement
Status Data
True
Valid Data
tACC
tRC
Note:
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read
cycle.
Figure 19.
Data# Polling Timings (During Embedded Algorithms)
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